cb0929bb13
M-profile CPUs generally allow configuration of the number of MPU regions that they have. We don't currently model this, so our implementations of some of the board models provide CPUs with the wrong number of regions. RTOSes like Zephyr that hardcode the expected number of regions may therefore not run on the model if they are set up to run on real hardware. Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, matching the ability of hardware to configure the number of Secure and NonSecure regions separately. Our actual CPU implementation doesn't currently support that, and it happens that none of the MPS boards we model set the number of regions differently for Secure vs NonSecure, so we provide an interface to the boards and SoCs that won't need to change if we ever do add that functionality in future, but make it an error to configure the two properties to different values. (The property name on the CPU is the somewhat misnamed-for-M-profile "pmsav7-dregion", so we don't follow that naming convention for the properties here. The TRM doesn't say what the CPU configuration variable names are, so we pick something, and follow the lowercase convention we already have for properties here.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
/*
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* ARMv7M CPU object
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*
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* Copyright (c) 2017 Linaro Ltd
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* Written by Peter Maydell <peter.maydell@linaro.org>
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*
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* This code is licensed under the GPL version 2 or later.
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*/
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#ifndef HW_ARM_ARMV7M_H
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#define HW_ARM_ARMV7M_H
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#include "hw/sysbus.h"
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#include "hw/intc/armv7m_nvic.h"
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#include "hw/misc/armv7m_ras.h"
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#include "target/arm/idau.h"
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#include "qom/object.h"
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#include "hw/clock.h"
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#define TYPE_BITBAND "ARM-bitband-memory"
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OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
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struct BitBandState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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AddressSpace source_as;
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MemoryRegion iomem;
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uint32_t base;
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MemoryRegion *source_memory;
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};
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#define TYPE_ARMV7M "armv7m"
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OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
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#define ARMV7M_NUM_BITBANDS 2
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/* ARMv7M container object.
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* + Unnamed GPIO input lines: external IRQ lines for the NVIC
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* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
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* If this GPIO is not wired up then the NVIC will default to performing
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* a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
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* + Property "cpu-type": CPU type to instantiate
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* + Property "num-irq": number of external IRQ lines
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* + Property "memory": MemoryRegion defining the physical address space
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* that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
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* devices will be automatically layered on top of this view.)
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* + Property "idau": IDAU interface (forwarded to CPU object)
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* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
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* + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object)
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* + Property "vfp": enable VFP (forwarded to CPU object)
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* + Property "dsp": enable DSP (forwarded to CPU object)
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* + Property "enable-bitband": expose bitbanded IO
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* + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
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* to CPU object pmsav7-dregion property; default is whatever the default
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* for the CPU is)
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* + Property "mpu-s-regions": number of Secure MPU regions (default is
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* whatever the default for the CPU is; must currently be set to the same
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* value as mpu-ns-regions if the CPU implements the Security Extension)
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* + Clock input "refclk" is the external reference clock for the systick timers
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* + Clock input "cpuclk" is the main CPU clock
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*/
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struct ARMv7MState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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NVICState nvic;
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BitBandState bitband[ARMV7M_NUM_BITBANDS];
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ARMCPU *cpu;
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ARMv7MRAS ras;
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SysTickState systick[M_REG_NUM_BANKS];
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/* MemoryRegion we pass to the CPU, with our devices layered on
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* top of the ones the board provides in board_memory.
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*/
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MemoryRegion container;
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/*
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* MemoryRegion which passes the transaction to either the S or the
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* NS systick device depending on the transaction attributes
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*/
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MemoryRegion systickmem;
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/*
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* MemoryRegion which enforces the S/NS handling of the systick
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* device NS alias region and passes the transaction to the
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* NS systick device if appropriate.
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*/
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MemoryRegion systick_ns_mem;
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/* Ditto, for the sysregs region provided by the NVIC */
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MemoryRegion sysreg_ns_mem;
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/* MR providing default PPB behaviour */
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MemoryRegion defaultmem;
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Clock *refclk;
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Clock *cpuclk;
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/* Properties */
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char *cpu_type;
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/* MemoryRegion the board provides to us (with its devices, RAM, etc) */
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MemoryRegion *board_memory;
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Object *idau;
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uint32_t init_svtor;
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uint32_t init_nsvtor;
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uint32_t mpu_ns_regions;
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uint32_t mpu_s_regions;
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bool enable_bitband;
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bool start_powered_off;
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bool vfp;
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bool dsp;
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};
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#endif
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