Bin Meng 4921a0ce86 hw/riscv: Move sifive_gpio model to hw/gpio ... This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory. Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-09-09 15:54:19 -07:00
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boot.c
Kconfig	hw/riscv: Move sifive_gpio model to hw/gpio	2020-09-09 15:54:19 -07:00
meson.build	hw/riscv: Move sifive_gpio model to hw/gpio	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: clint: Avoid using hard-coded timebase frequency	2020-09-09 15:54:19 -07:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	target/riscv: cpu: Set reset vector based on the configured property value	2020-09-09 15:54:18 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
riscv_htif.c
sifive_clint.c	hw/riscv: clint: Avoid using hard-coded timebase frequency	2020-09-09 15:54:19 -07:00
sifive_e.c	hw/riscv: Move sifive_e_prci model to hw/misc	2020-09-09 15:54:19 -07:00
sifive_plic.c	hw/riscv: Allow creating multiple instances of PLIC	2020-08-25 09:11:35 -07:00
sifive_test.c	riscv: sifive_test: Allow 16-bit writes to memory region	2020-09-09 15:54:18 -07:00
sifive_u.c	hw/riscv: sifive_u: Connect a DMA controller	2020-09-09 15:54:19 -07:00
sifive_uart.c
spike.c	hw/riscv: clint: Avoid using hard-coded timebase frequency	2020-09-09 15:54:19 -07:00
virt.c	hw/riscv: clint: Avoid using hard-coded timebase frequency	2020-09-09 15:54:19 -07:00