321 lines
8.8 KiB
C
321 lines
8.8 KiB
C
/*
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* BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
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* Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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* Based on pl011.c, copyright terms below:
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*
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* Arm PrimeCell PL011 UART
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*
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* At present only the core UART functions (data path for tx/rx) are
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* implemented. The following features/registers are unimplemented:
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* - Line/modem control
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* - Scratch register
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* - Extra control
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* - Baudrate
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* - SPI interfaces
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*/
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#include "qemu/osdep.h"
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#include "hw/char/bcm2835_aux.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define AUX_IRQ 0x0
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#define AUX_ENABLES 0x4
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#define AUX_MU_IO_REG 0x40
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#define AUX_MU_IER_REG 0x44
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#define AUX_MU_IIR_REG 0x48
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#define AUX_MU_LCR_REG 0x4c
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#define AUX_MU_MCR_REG 0x50
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#define AUX_MU_LSR_REG 0x54
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#define AUX_MU_MSR_REG 0x58
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#define AUX_MU_SCRATCH 0x5c
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#define AUX_MU_CNTL_REG 0x60
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#define AUX_MU_STAT_REG 0x64
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#define AUX_MU_BAUD_REG 0x68
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/* bits in IER/IIR registers */
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#define RX_INT 0x1
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#define TX_INT 0x2
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static void bcm2835_aux_update(BCM2835AuxState *s)
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{
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/* signal an interrupt if either:
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* 1. rx interrupt is enabled and we have a non-empty rx fifo, or
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* 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
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*/
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s->iir = 0;
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if ((s->ier & RX_INT) && s->read_count != 0) {
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s->iir |= RX_INT;
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}
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if (s->ier & TX_INT) {
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s->iir |= TX_INT;
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}
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qemu_set_irq(s->irq, s->iir != 0);
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}
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static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
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{
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BCM2835AuxState *s = opaque;
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uint32_t c, res;
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switch (offset) {
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case AUX_IRQ:
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return s->iir != 0;
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case AUX_ENABLES:
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return 1; /* mini UART permanently enabled */
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case AUX_MU_IO_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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c = s->read_fifo[s->read_pos];
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if (s->read_count > 0) {
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s->read_count--;
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if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
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s->read_pos = 0;
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}
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}
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qemu_chr_fe_accept_input(&s->chr);
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bcm2835_aux_update(s);
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return c;
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case AUX_MU_IER_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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return 0xc0 | s->ier; /* FIFO enables always read 1 */
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case AUX_MU_IIR_REG:
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res = 0xc0; /* FIFO enables */
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/* The spec is unclear on what happens when both tx and rx
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* interrupts are active, besides that this cannot occur. At
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* present, we choose to prioritise the rx interrupt, since
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* the tx fifo is always empty. */
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if (s->read_count != 0) {
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res |= 0x4;
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} else {
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res |= 0x2;
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}
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if (s->iir == 0) {
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res |= 0x1;
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}
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return res;
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case AUX_MU_LCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
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return 0;
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case AUX_MU_MCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
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return 0;
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case AUX_MU_LSR_REG:
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res = 0x60; /* tx idle, empty */
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if (s->read_count != 0) {
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res |= 0x1;
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}
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return res;
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case AUX_MU_MSR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
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return 0;
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case AUX_MU_SCRATCH:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
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return 0;
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case AUX_MU_CNTL_REG:
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return 0x3; /* tx, rx enabled */
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case AUX_MU_STAT_REG:
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res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
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if (s->read_count > 0) {
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res |= 0x1; /* data in input buffer */
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assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
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res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
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}
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return res;
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case AUX_MU_BAUD_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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return 0;
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}
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}
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static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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BCM2835AuxState *s = opaque;
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unsigned char ch;
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switch (offset) {
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case AUX_ENABLES:
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if (value != 1) {
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qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI"
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" or disable UART: 0x%"PRIx64"\n",
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__func__, value);
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}
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break;
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case AUX_MU_IO_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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ch = value;
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/* XXX this blocks entire thread. Rewrite to use
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* qemu_chr_fe_write and background I/O callbacks */
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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break;
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case AUX_MU_IER_REG:
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/* "DLAB bit set means access baudrate register" is NYI */
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s->ier = value & (TX_INT | RX_INT);
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bcm2835_aux_update(s);
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break;
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case AUX_MU_IIR_REG:
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if (value & 0x2) {
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s->read_count = 0;
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}
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break;
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case AUX_MU_LCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
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break;
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case AUX_MU_MCR_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
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break;
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case AUX_MU_SCRATCH:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
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break;
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case AUX_MU_CNTL_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
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break;
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case AUX_MU_BAUD_REG:
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qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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}
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bcm2835_aux_update(s);
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}
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static int bcm2835_aux_can_receive(void *opaque)
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{
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BCM2835AuxState *s = opaque;
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return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
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}
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static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
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{
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BCM2835AuxState *s = opaque;
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int slot;
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slot = s->read_pos + s->read_count;
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if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
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slot -= BCM2835_AUX_RX_FIFO_LEN;
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}
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s->read_fifo[slot] = value;
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s->read_count++;
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if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
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/* buffer full */
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}
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bcm2835_aux_update(s);
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}
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static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
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{
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bcm2835_aux_put_fifo(opaque, *buf);
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}
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static const MemoryRegionOps bcm2835_aux_ops = {
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.read = bcm2835_aux_read,
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.write = bcm2835_aux_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription vmstate_bcm2835_aux = {
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.name = TYPE_BCM2835_AUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
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BCM2835_AUX_RX_FIFO_LEN),
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VMSTATE_UINT8(read_pos, BCM2835AuxState),
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VMSTATE_UINT8(read_count, BCM2835AuxState),
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VMSTATE_UINT8(ier, BCM2835AuxState),
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VMSTATE_UINT8(iir, BCM2835AuxState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2835_aux_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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BCM2835AuxState *s = BCM2835_AUX(obj);
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memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
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TYPE_BCM2835_AUX, 0x100);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
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{
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BCM2835AuxState *s = BCM2835_AUX(dev);
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qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
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bcm2835_aux_receive, NULL, NULL, s, NULL, true);
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}
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static Property bcm2835_aux_props[] = {
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DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void bcm2835_aux_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = bcm2835_aux_realize;
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dc->vmsd = &vmstate_bcm2835_aux;
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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device_class_set_props(dc, bcm2835_aux_props);
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}
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static const TypeInfo bcm2835_aux_info = {
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.name = TYPE_BCM2835_AUX,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835AuxState),
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.instance_init = bcm2835_aux_init,
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.class_init = bcm2835_aux_class_init,
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};
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static void bcm2835_aux_register_types(void)
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{
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type_register_static(&bcm2835_aux_info);
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}
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type_init(bcm2835_aux_register_types)
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