qemu-e2k/target-mips
aurel32 49bcf33cc7 target-mips: convert bit shuffle ops to TCG
Bit shuffle operations can be written with very few TCG instructions
(between 5 and 8), so it is worth converting them to TCG.

This code also move all bit shuffle generation code to a separate
function in order to have a cleaner exception code path, that is it
doesn't store back the TCG register to the target register after the
exception, as the TCG register doesn't exist anymore.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5679 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11 11:47:06 +00:00
..
cpu.h target-mips: optimize gen_op_addr_add() (2/2) 2008-11-11 11:39:33 +00:00
exec.h target-mips: optimize gen_op_addr_add() (2/2) 2008-11-11 11:39:33 +00:00
helper.c Fix Xcontext fill, by Here Poussineau. 2008-09-21 21:21:26 +00:00
helper.h target-mips: convert bit shuffle ops to TCG 2008-11-11 11:47:06 +00:00
machine.c Change MIPS machine default to Malta. 2008-07-05 21:51:47 +00:00
mips-defs.h Support for VR5432, and some of its special instructions. Original patch 2007-12-25 20:46:56 +00:00
op_helper.c target-mips: convert bit shuffle ops to TCG 2008-11-11 11:47:06 +00:00
TODO Move the active FPU registers into env again, and use more TCG registers 2008-09-18 11:57:27 +00:00
translate_init.c Move the active FPU registers into env again, and use more TCG registers 2008-09-18 11:57:27 +00:00
translate.c target-mips: convert bit shuffle ops to TCG 2008-11-11 11:47:06 +00:00