fa439fc5d7
The ARM architecture defines that the "IS" variants of TLB maintenance operations must affect all TLBs in the Inner Shareable domain, which for us means all CPUs. We were incorrectly implementing these to only affect the current CPU, which meant that SMP TCG operation was unstable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org |
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| .. | ||
| arm_ldst.h | ||
| arm-semi.c | ||
| cpu64.c | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| crypto_helper.c | ||
| gdbstub64.c | ||
| gdbstub.c | ||
| helper-a64.c | ||
| helper-a64.h | ||
| helper.c | ||
| helper.h | ||
| internals.h | ||
| iwmmxt_helper.c | ||
| kvm32.c | ||
| kvm64.c | ||
| kvm_arm.h | ||
| kvm-consts.h | ||
| kvm-stub.c | ||
| kvm.c | ||
| machine.c | ||
| Makefile.objs | ||
| neon_helper.c | ||
| op_addsub.h | ||
| op_helper.c | ||
| translate-a64.c | ||
| translate.c | ||
| translate.h | ||