qemu-e2k/include/hw/char
Laurent Vivier b43047a20f escc: introduce a selector for the register bit
On Sparc and PowerMac, the bit 0 of the address selects the register
type (control or data) and bit 1 selects the channel (B or A).

On m68k Macintosh and NeXTcube, the bit 0 selects the channel and
bit 1 the register type.

This patch introduces a new parameter (bit_swap) to the device interface
to indicate bits usage must be swapped between registers and channels.

For the moment all the machines use the bit 0, but this change will be
needed to emulate the Quadra 800 or NeXTcube machine.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
[thh: added NeXTcube to the patch description]
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190831074519.32613-5-huth@tuxfamily.org>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2019-09-07 08:32:12 +02:00
..
bcm2835_aux.h char: move CharBackend handling in char-fe unit 2017-06-02 11:33:53 +04:00
cadence_uart.h Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00
cmsdk-apb-uart.h Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00
digic-uart.h char: move CharBackend handling in char-fe unit 2017-06-02 11:33:53 +04:00
escc.h escc: introduce a selector for the register bit 2019-09-07 08:32:12 +02:00
imx_serial.h imx_serial: Generate interrupt on receive data ready if enabled 2018-08-20 11:24:31 +01:00
lm32_juart.h Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00
nrf51_uart.h arm: Add header to host common definition for nRF51 SOC peripherals 2019-01-07 15:23:47 +00:00
parallel.h Include exec/memory.h slightly less 2019-08-16 13:31:52 +02:00
pl011.h Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00
serial.h Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00
stm32f2xx_usart.h Include hw/hw.h exactly where needed 2019-08-16 13:31:52 +02:00
xilinx_uartlite.h Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00