7a426f83c3
Updates the `EVENT_ENABLE` register to offset `0x34` as per OpenTitan spec [1]. [1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220823061201.132342-5-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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.. | ||
aspeed_smc.c | ||
ibex_spi_host.c | ||
imx_spi.c | ||
Kconfig | ||
meson.build | ||
mss-spi.c | ||
npcm7xx_fiu.c | ||
omap_spi.c | ||
pl022.c | ||
sifive_spi.c | ||
ssi.c | ||
stm32f2xx_spi.c | ||
trace-events | ||
trace.h | ||
xilinx_spi.c | ||
xilinx_spips.c | ||
xlnx-versal-ospi.c |