648 lines
16 KiB
C
648 lines
16 KiB
C
/*
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* x86 misc helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/ioport.h"
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#include "helper.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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/* check if Port I/O is allowed in TSS */
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static inline void check_io(CPUX86State *env, int addr, int size)
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{
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int io_offset, val, mask;
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/* TSS must be a valid 32 bit one */
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if (!(env->tr.flags & DESC_P_MASK) ||
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((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
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env->tr.limit < 103) {
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goto fail;
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}
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io_offset = cpu_lduw_kernel(env, env->tr.base + 0x66);
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io_offset += (addr >> 3);
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/* Note: the check needs two bytes */
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if ((io_offset + 1) > env->tr.limit) {
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goto fail;
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}
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val = cpu_lduw_kernel(env, env->tr.base + io_offset);
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val >>= (addr & 7);
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mask = (1 << size) - 1;
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/* all bits must be zero to allow the I/O */
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if ((val & mask) != 0) {
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fail:
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raise_exception_err(env, EXCP0D_GPF, 0);
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}
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}
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void helper_check_iob(CPUX86State *env, uint32_t t0)
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{
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check_io(env, t0, 1);
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}
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void helper_check_iow(CPUX86State *env, uint32_t t0)
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{
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check_io(env, t0, 2);
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}
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void helper_check_iol(CPUX86State *env, uint32_t t0)
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{
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check_io(env, t0, 4);
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}
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void helper_outb(uint32_t port, uint32_t data)
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{
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cpu_outb(port, data & 0xff);
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}
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target_ulong helper_inb(uint32_t port)
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{
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return cpu_inb(port);
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}
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void helper_outw(uint32_t port, uint32_t data)
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{
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cpu_outw(port, data & 0xffff);
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}
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target_ulong helper_inw(uint32_t port)
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{
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return cpu_inw(port);
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}
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void helper_outl(uint32_t port, uint32_t data)
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{
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cpu_outl(port, data);
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}
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target_ulong helper_inl(uint32_t port)
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{
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return cpu_inl(port);
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}
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void helper_into(CPUX86State *env, int next_eip_addend)
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{
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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if (eflags & CC_O) {
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raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
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}
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}
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void helper_single_step(CPUX86State *env)
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{
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#ifndef CONFIG_USER_ONLY
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check_hw_breakpoints(env, true);
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(env, EXCP01_DB);
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}
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void helper_cpuid(CPUX86State *env)
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{
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uint32_t eax, ebx, ecx, edx;
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cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
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cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
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&eax, &ebx, &ecx, &edx);
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env->regs[R_EAX] = eax;
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env->regs[R_EBX] = ebx;
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env->regs[R_ECX] = ecx;
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env->regs[R_EDX] = edx;
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}
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#if defined(CONFIG_USER_ONLY)
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target_ulong helper_read_crN(CPUX86State *env, int reg)
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{
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return 0;
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}
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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{
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}
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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{
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}
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#else
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target_ulong helper_read_crN(CPUX86State *env, int reg)
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{
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target_ulong val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
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switch (reg) {
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default:
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val = env->cr[reg];
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break;
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case 8:
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
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} else {
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val = env->v_tpr;
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}
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break;
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}
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return val;
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}
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
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switch (reg) {
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case 0:
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cpu_x86_update_cr0(env, t0);
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break;
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case 3:
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cpu_x86_update_cr3(env, t0);
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break;
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case 4:
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cpu_x86_update_cr4(env, t0);
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break;
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case 8:
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
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}
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env->v_tpr = t0 & 0x0f;
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break;
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default:
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env->cr[reg] = t0;
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break;
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}
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}
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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{
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int i;
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if (reg < 4) {
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hw_breakpoint_remove(env, reg);
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env->dr[reg] = t0;
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hw_breakpoint_insert(env, reg);
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} else if (reg == 7) {
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_remove(env, i);
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}
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env->dr[7] = t0;
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for (i = 0; i < DR7_MAX_BP; i++) {
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hw_breakpoint_insert(env, i);
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}
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} else {
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env->dr[reg] = t0;
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}
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}
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#endif
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void helper_lmsw(CPUX86State *env, target_ulong t0)
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{
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/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
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if already set to one. */
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t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
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helper_write_crN(env, 0, t0);
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}
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void helper_invlpg(CPUX86State *env, target_ulong addr)
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{
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X86CPU *cpu = x86_env_get_cpu(env);
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cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
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tlb_flush_page(CPU(cpu), addr);
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}
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void helper_rdtsc(CPUX86State *env)
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{
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uint64_t val;
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if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
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raise_exception(env, EXCP0D_GPF);
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}
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cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
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val = cpu_get_tsc(env) + env->tsc_offset;
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env->regs[R_EAX] = (uint32_t)(val);
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env->regs[R_EDX] = (uint32_t)(val >> 32);
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}
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void helper_rdtscp(CPUX86State *env)
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{
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helper_rdtsc(env);
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env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
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}
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void helper_rdpmc(CPUX86State *env)
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{
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if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
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raise_exception(env, EXCP0D_GPF);
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}
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cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
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/* currently unimplemented */
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qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
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raise_exception_err(env, EXCP06_ILLOP, 0);
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}
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#if defined(CONFIG_USER_ONLY)
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void helper_wrmsr(CPUX86State *env)
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{
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}
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void helper_rdmsr(CPUX86State *env)
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{
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}
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#else
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void helper_wrmsr(CPUX86State *env)
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{
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uint64_t val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
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val = ((uint32_t)env->regs[R_EAX]) |
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((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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switch ((uint32_t)env->regs[R_ECX]) {
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case MSR_IA32_SYSENTER_CS:
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env->sysenter_cs = val & 0xffff;
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break;
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case MSR_IA32_SYSENTER_ESP:
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env->sysenter_esp = val;
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break;
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case MSR_IA32_SYSENTER_EIP:
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env->sysenter_eip = val;
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break;
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case MSR_IA32_APICBASE:
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cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
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break;
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case MSR_EFER:
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{
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uint64_t update_mask;
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update_mask = 0;
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
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update_mask |= MSR_EFER_SCE;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
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update_mask |= MSR_EFER_LME;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
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update_mask |= MSR_EFER_FFXSR;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
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update_mask |= MSR_EFER_NXE;
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}
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if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
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update_mask |= MSR_EFER_SVME;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
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update_mask |= MSR_EFER_FFXSR;
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}
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cpu_load_efer(env, (env->efer & ~update_mask) |
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(val & update_mask));
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}
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break;
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case MSR_STAR:
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env->star = val;
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break;
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case MSR_PAT:
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env->pat = val;
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break;
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case MSR_VM_HSAVE_PA:
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env->vm_hsave = val;
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break;
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#ifdef TARGET_X86_64
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case MSR_LSTAR:
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env->lstar = val;
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break;
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case MSR_CSTAR:
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env->cstar = val;
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break;
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case MSR_FMASK:
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env->fmask = val;
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break;
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case MSR_FSBASE:
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env->segs[R_FS].base = val;
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break;
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case MSR_GSBASE:
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env->segs[R_GS].base = val;
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break;
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case MSR_KERNELGSBASE:
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env->kernelgsbase = val;
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break;
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#endif
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case MSR_MTRRphysBase(0):
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case MSR_MTRRphysBase(1):
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case MSR_MTRRphysBase(2):
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case MSR_MTRRphysBase(3):
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case MSR_MTRRphysBase(4):
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case MSR_MTRRphysBase(5):
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case MSR_MTRRphysBase(6):
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case MSR_MTRRphysBase(7):
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env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysBase(0)) / 2].base = val;
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break;
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case MSR_MTRRphysMask(0):
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case MSR_MTRRphysMask(1):
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case MSR_MTRRphysMask(2):
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case MSR_MTRRphysMask(3):
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case MSR_MTRRphysMask(4):
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case MSR_MTRRphysMask(5):
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case MSR_MTRRphysMask(6):
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case MSR_MTRRphysMask(7):
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env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysMask(0)) / 2].mask = val;
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break;
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case MSR_MTRRfix64K_00000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix64K_00000] = val;
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break;
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case MSR_MTRRfix16K_80000:
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case MSR_MTRRfix16K_A0000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix16K_80000 + 1] = val;
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break;
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case MSR_MTRRfix4K_C0000:
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case MSR_MTRRfix4K_C8000:
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case MSR_MTRRfix4K_D0000:
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case MSR_MTRRfix4K_D8000:
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case MSR_MTRRfix4K_E0000:
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case MSR_MTRRfix4K_E8000:
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case MSR_MTRRfix4K_F0000:
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case MSR_MTRRfix4K_F8000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix4K_C0000 + 3] = val;
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break;
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case MSR_MTRRdefType:
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env->mtrr_deftype = val;
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break;
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case MSR_MCG_STATUS:
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env->mcg_status = val;
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break;
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case MSR_MCG_CTL:
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if ((env->mcg_cap & MCG_CTL_P)
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&& (val == 0 || val == ~(uint64_t)0)) {
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env->mcg_ctl = val;
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}
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break;
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case MSR_TSC_AUX:
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env->tsc_aux = val;
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break;
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case MSR_IA32_MISC_ENABLE:
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env->msr_ia32_misc_enable = val;
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break;
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default:
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if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
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(4 * env->mcg_cap & 0xff)) {
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uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
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if ((offset & 0x3) != 0
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|| (val == 0 || val == ~(uint64_t)0)) {
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env->mce_banks[offset] = val;
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}
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break;
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}
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/* XXX: exception? */
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break;
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}
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}
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void helper_rdmsr(CPUX86State *env)
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{
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uint64_t val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
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switch ((uint32_t)env->regs[R_ECX]) {
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case MSR_IA32_SYSENTER_CS:
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val = env->sysenter_cs;
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break;
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case MSR_IA32_SYSENTER_ESP:
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val = env->sysenter_esp;
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break;
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case MSR_IA32_SYSENTER_EIP:
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val = env->sysenter_eip;
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break;
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case MSR_IA32_APICBASE:
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val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
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break;
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case MSR_EFER:
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val = env->efer;
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break;
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case MSR_STAR:
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val = env->star;
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break;
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case MSR_PAT:
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val = env->pat;
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break;
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case MSR_VM_HSAVE_PA:
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val = env->vm_hsave;
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break;
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case MSR_IA32_PERF_STATUS:
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/* tsc_increment_by_tick */
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val = 1000ULL;
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/* CPU multiplier */
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val |= (((uint64_t)4ULL) << 40);
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break;
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#ifdef TARGET_X86_64
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case MSR_LSTAR:
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val = env->lstar;
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break;
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case MSR_CSTAR:
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val = env->cstar;
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break;
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case MSR_FMASK:
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val = env->fmask;
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break;
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case MSR_FSBASE:
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val = env->segs[R_FS].base;
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break;
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case MSR_GSBASE:
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val = env->segs[R_GS].base;
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break;
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case MSR_KERNELGSBASE:
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val = env->kernelgsbase;
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break;
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case MSR_TSC_AUX:
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val = env->tsc_aux;
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break;
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#endif
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case MSR_MTRRphysBase(0):
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case MSR_MTRRphysBase(1):
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case MSR_MTRRphysBase(2):
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case MSR_MTRRphysBase(3):
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case MSR_MTRRphysBase(4):
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case MSR_MTRRphysBase(5):
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case MSR_MTRRphysBase(6):
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case MSR_MTRRphysBase(7):
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysBase(0)) / 2].base;
|
|
break;
|
|
case MSR_MTRRphysMask(0):
|
|
case MSR_MTRRphysMask(1):
|
|
case MSR_MTRRphysMask(2):
|
|
case MSR_MTRRphysMask(3):
|
|
case MSR_MTRRphysMask(4):
|
|
case MSR_MTRRphysMask(5):
|
|
case MSR_MTRRphysMask(6):
|
|
case MSR_MTRRphysMask(7):
|
|
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
|
|
MSR_MTRRphysMask(0)) / 2].mask;
|
|
break;
|
|
case MSR_MTRRfix64K_00000:
|
|
val = env->mtrr_fixed[0];
|
|
break;
|
|
case MSR_MTRRfix16K_80000:
|
|
case MSR_MTRRfix16K_A0000:
|
|
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
MSR_MTRRfix16K_80000 + 1];
|
|
break;
|
|
case MSR_MTRRfix4K_C0000:
|
|
case MSR_MTRRfix4K_C8000:
|
|
case MSR_MTRRfix4K_D0000:
|
|
case MSR_MTRRfix4K_D8000:
|
|
case MSR_MTRRfix4K_E0000:
|
|
case MSR_MTRRfix4K_E8000:
|
|
case MSR_MTRRfix4K_F0000:
|
|
case MSR_MTRRfix4K_F8000:
|
|
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
MSR_MTRRfix4K_C0000 + 3];
|
|
break;
|
|
case MSR_MTRRdefType:
|
|
val = env->mtrr_deftype;
|
|
break;
|
|
case MSR_MTRRcap:
|
|
if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
|
|
val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
|
|
MSR_MTRRcap_WC_SUPPORTED;
|
|
} else {
|
|
/* XXX: exception? */
|
|
val = 0;
|
|
}
|
|
break;
|
|
case MSR_MCG_CAP:
|
|
val = env->mcg_cap;
|
|
break;
|
|
case MSR_MCG_CTL:
|
|
if (env->mcg_cap & MCG_CTL_P) {
|
|
val = env->mcg_ctl;
|
|
} else {
|
|
val = 0;
|
|
}
|
|
break;
|
|
case MSR_MCG_STATUS:
|
|
val = env->mcg_status;
|
|
break;
|
|
case MSR_IA32_MISC_ENABLE:
|
|
val = env->msr_ia32_misc_enable;
|
|
break;
|
|
default:
|
|
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
|
|
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
|
|
(4 * env->mcg_cap & 0xff)) {
|
|
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
|
|
val = env->mce_banks[offset];
|
|
break;
|
|
}
|
|
/* XXX: exception? */
|
|
val = 0;
|
|
break;
|
|
}
|
|
env->regs[R_EAX] = (uint32_t)(val);
|
|
env->regs[R_EDX] = (uint32_t)(val >> 32);
|
|
}
|
|
#endif
|
|
|
|
static void do_pause(X86CPU *cpu)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
/* Just let another CPU run. */
|
|
cs->exception_index = EXCP_INTERRUPT;
|
|
cpu_loop_exit(cs);
|
|
}
|
|
|
|
static void do_hlt(X86CPU *cpu)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
|
|
cs->halted = 1;
|
|
cs->exception_index = EXCP_HLT;
|
|
cpu_loop_exit(cs);
|
|
}
|
|
|
|
void helper_hlt(CPUX86State *env, int next_eip_addend)
|
|
{
|
|
X86CPU *cpu = x86_env_get_cpu(env);
|
|
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
|
|
env->eip += next_eip_addend;
|
|
|
|
do_hlt(cpu);
|
|
}
|
|
|
|
void helper_monitor(CPUX86State *env, target_ulong ptr)
|
|
{
|
|
if ((uint32_t)env->regs[R_ECX] != 0) {
|
|
raise_exception(env, EXCP0D_GPF);
|
|
}
|
|
/* XXX: store address? */
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
|
|
}
|
|
|
|
void helper_mwait(CPUX86State *env, int next_eip_addend)
|
|
{
|
|
CPUState *cs;
|
|
X86CPU *cpu;
|
|
|
|
if ((uint32_t)env->regs[R_ECX] != 0) {
|
|
raise_exception(env, EXCP0D_GPF);
|
|
}
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
|
|
env->eip += next_eip_addend;
|
|
|
|
cpu = x86_env_get_cpu(env);
|
|
cs = CPU(cpu);
|
|
/* XXX: not complete but not completely erroneous */
|
|
if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
|
|
do_pause(cpu);
|
|
} else {
|
|
do_hlt(cpu);
|
|
}
|
|
}
|
|
|
|
void helper_pause(CPUX86State *env, int next_eip_addend)
|
|
{
|
|
X86CPU *cpu = x86_env_get_cpu(env);
|
|
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0);
|
|
env->eip += next_eip_addend;
|
|
|
|
do_pause(cpu);
|
|
}
|
|
|
|
void helper_debug(CPUX86State *env)
|
|
{
|
|
CPUState *cs = CPU(x86_env_get_cpu(env));
|
|
|
|
cs->exception_index = EXCP_DEBUG;
|
|
cpu_loop_exit(cs);
|
|
}
|