edf5ca5dbe
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
/*
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* QEMU VMWARE VMXNET3 paravirtual NIC
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*
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* Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
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*
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Dmitry Fleytman <dmitry@daynix.com>
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* Tamir Shomer <tamirs@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef HW_NET_VMXNET3_DEFS_H
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#define HW_NET_VMXNET3_DEFS_H
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#include "net/net.h"
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#include "hw/net/vmxnet3.h"
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#include "hw/pci/pci_device.h"
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#define TYPE_VMXNET3 "vmxnet3"
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typedef struct VMXNET3State VMXNET3State;
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DECLARE_INSTANCE_CHECKER(VMXNET3State, VMXNET3,
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TYPE_VMXNET3)
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/* Device state and helper functions */
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#define VMXNET3_RX_RINGS_PER_QUEUE (2)
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/* Cyclic ring abstraction */
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typedef struct {
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hwaddr pa;
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uint32_t size;
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uint32_t cell_size;
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uint32_t next;
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uint8_t gen;
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} Vmxnet3Ring;
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typedef struct {
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Vmxnet3Ring tx_ring;
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Vmxnet3Ring comp_ring;
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uint8_t intr_idx;
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hwaddr tx_stats_pa;
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struct UPT1_TxStats txq_stats;
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} Vmxnet3TxqDescr;
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typedef struct {
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Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
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Vmxnet3Ring comp_ring;
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uint8_t intr_idx;
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hwaddr rx_stats_pa;
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struct UPT1_RxStats rxq_stats;
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} Vmxnet3RxqDescr;
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typedef struct {
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bool is_masked;
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bool is_pending;
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bool is_asserted;
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} Vmxnet3IntState;
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struct VMXNET3State {
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PCIDevice parent_obj;
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NICState *nic;
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NICConf conf;
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MemoryRegion bar0;
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MemoryRegion bar1;
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MemoryRegion msix_bar;
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Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
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Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
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/* Whether MSI-X support was installed successfully */
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bool msix_used;
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hwaddr drv_shmem;
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hwaddr temp_shared_guest_driver_memory;
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uint8_t txq_num;
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/* This boolean tells whether RX packet being indicated has to */
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/* be split into head and body chunks from different RX rings */
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bool rx_packets_compound;
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bool rx_vlan_stripping;
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bool lro_supported;
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uint8_t rxq_num;
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/* Network MTU */
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uint32_t mtu;
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/* Maximum number of fragments for indicated TX packets */
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uint32_t max_tx_frags;
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/* Maximum number of fragments for indicated RX packets */
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uint16_t max_rx_frags;
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/* Index for events interrupt */
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uint8_t event_int_idx;
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/* Whether automatic interrupts masking enabled */
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bool auto_int_masking;
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bool peer_has_vhdr;
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/* TX packets to QEMU interface */
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struct NetTxPkt *tx_pkt;
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uint32_t offload_mode;
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uint32_t cso_or_gso_size;
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uint16_t tci;
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bool needs_vlan;
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struct NetRxPkt *rx_pkt;
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bool tx_sop;
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bool skip_current_tx_pkt;
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uint32_t device_active;
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uint32_t last_command;
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uint32_t link_status_and_speed;
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Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
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uint32_t temp_mac; /* To store the low part first */
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MACAddr perm_mac;
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uint32_t vlan_table[VMXNET3_VFT_SIZE];
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uint32_t rx_mode;
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MACAddr *mcast_list;
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uint32_t mcast_list_len;
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uint32_t mcast_list_buff_size; /* needed for live migration. */
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/* Compatibility flags for migration */
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uint32_t compat_flags;
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};
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#endif
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