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qemu-e2k/hw/riscv
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Tsukasa OI 4bcfc391ac hw/riscv: Make CPU config error handling generous (virt/spike) 
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system).  This kind of error handling should be used only when a serious
runtime error occurs.

This commit makes error handling on CPU configuration more generous on
virt/spike machines.  It now just prints error message and quits (without
coredumps and aborts).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2022-05-24 10:38:50 +10:00
..
Kconfig hw/riscv: Enable TPM backends 2022-04-29 10:48:48 +10:00
boot.c hw/riscv: boot: Support 64bit fdt address. 2022-04-22 10:35:16 +10:00
meson.build hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines 2021-07-20 15:32:49 +02:00
microchip_pfsoc.c hw/riscv: Don't add empty bootargs to device tree 2022-04-29 10:47:45 +10:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c riscv: opentitan: Connect opentitan SPI Host 2022-04-22 10:35:16 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id 2021-10-22 23:35:47 +10:00
sifive_e.c hw/riscv: Use error_fatal for SoC realisation 2022-01-08 15:46:09 +10:00
sifive_u.c hw/riscv: Don't add empty bootargs to device tree 2022-04-29 10:47:45 +10:00
spike.c hw/riscv: Make CPU config error handling generous (virt/spike) 2022-05-24 10:38:50 +10:00
virt.c hw/riscv: Make CPU config error handling generous (virt/spike) 2022-05-24 10:38:50 +10:00