4c25f365ab
To make it consistent for easier code reading. The order in which variables are defined and functions are called is set to match the address map ordering. The new consistent order of doing stuff is: SCU -> GIC -> MPTimer -> WDT. 0 functional change. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8f31398e6d9a93f57291399f269039da1a77a2b5.1385969450.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38 lines
807 B
C
38 lines
807 B
C
/*
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* Cortex-A9MPCore internal peripheral emulation.
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*
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* Copyright (c) 2009 CodeSourcery.
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* Copyright (c) 2011 Linaro Limited.
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* Written by Paul Brook, Peter Maydell.
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*
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* This code is licensed under the GPL.
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*/
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#ifndef HW_CPU_A9MPCORE_H
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#define HW_CPU_A9MPCORE_H
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#include "hw/sysbus.h"
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#include "hw/intc/arm_gic.h"
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#include "hw/misc/a9scu.h"
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#include "hw/timer/arm_mptimer.h"
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#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
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#define A9MPCORE_PRIV(obj) \
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OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV)
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typedef struct A9MPPrivState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t num_cpu;
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MemoryRegion container;
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uint32_t num_irq;
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A9SCUState scu;
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GICState gic;
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ARMMPTimerState mptimer;
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ARMMPTimerState wdt;
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} A9MPPrivState;
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#endif
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