Peter Maydell e4d51ac692 target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns ... In commit cd8be50e58 we converted the A32 coprocessor insns to decodetree. This accidentally broke XScale/iWMMXt insns, because it moved the handling of "cp insns which are handled by looking up the cp register in the hashtable" from after the call to the legacy disas_xscale_insn() decode to before it, with the result that all XScale/iWMMXt insns now UNDEF. Update valid_cp() so that it knows that on XScale cp 0 and 1 are not standard coprocessor instructions; this will cause the decodetree trans_ functions to ignore them, so that execution will correctly get through to the legacy decode again. Cc: qemu-stable@nongnu.org Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20210108195157.32067-1-peter.maydell@linaro.org		2021-01-12 21:19:02 +00:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
arm-semi.c	arm: do not use ram_size global	2020-12-10 12:15:07 -05:00
cpu64.c	target/arm: enable Small Translation tables in max CPU	2021-01-12 10:04:10 +00:00
cpu_tcg.c	target/arm: Implement Cortex-M55 model	2021-01-08 15:13:38 +00:00
cpu-param.h
cpu-qom.h
cpu.c	target/arm: Remove timer_del()/timer_deinit() before timer_free()	2021-01-08 15:13:38 +00:00
cpu.h	target/arm: add aarch32 ID register fields to cpu.h	2021-01-12 10:09:14 +00:00
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper-sve.h
helper.c	target/arm: ARMv8.4-TTST extension	2021-01-12 10:03:04 +00:00
helper.h
idau.h
internals.h
iwmmxt_helper.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
m_helper.c	target/arm: Implement CCR_S.TRD behaviour for SG insns	2020-12-10 11:44:56 +00:00
m-nocp.decode	target/arm: Implement new v8.1M VLLDM and VLSTM encodings	2020-12-10 11:44:56 +00:00
machine.c	migration: Replace migration's JSON writer by the general one	2020-12-19 10:39:16 +01:00
meson.build
monitor.c	qapi: Use QAPI_LIST_PREPEND() where possible	2020-12-19 10:20:14 +01:00
mte_helper.c
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c
pauth_helper.c
psci.c
sve_helper.c
sve.decode
t16.decode
t32.decode	target/arm: Implement M-profile "minimal RAS implementation"	2020-12-10 11:44:56 +00:00
tlb_helper.c
trace-events
trace.h
translate-a64.c	tcg: Make DisasContextBase.tb const	2021-01-07 05:09:41 -10:00
translate-a64.h
translate-neon.c.inc
translate-sve.c
translate-vfp.c.inc	target/arm: Implement FPCXT_NS fp system register	2021-01-08 15:13:38 +00:00
translate.c	target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns	2021-01-12 21:19:02 +00:00
translate.h
vec_helper.c
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode	target/arm: Implement VLDR/VSTR system register	2020-12-10 11:44:55 +00:00