qemu-e2k/target
Peter Maydell 4c498dcfd8 target/arm: Convert T32 coprocessor insns to decodetree
Convert the T32 coprocessor instructions to decodetree.
As with the A32 conversion, this corrects an underdecoding
where we did not check that MRRC/MCRR [24:21] were 0b0010
and so treated some kinds of LDC/STC and MRRC/MCRR rather
than UNDEFing them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-7-peter.maydell@linaro.org
2020-08-24 10:15:08 +01:00
..
alpha meson: target 2020-08-21 06:30:35 -04:00
arm target/arm: Convert T32 coprocessor insns to decodetree 2020-08-24 10:15:08 +01:00
avr meson: target 2020-08-21 06:30:35 -04:00
cris meson: target 2020-08-21 06:30:35 -04:00
hppa meson: target 2020-08-21 06:30:35 -04:00
i386 meson: target 2020-08-21 06:30:35 -04:00
lm32 meson: target 2020-08-21 06:30:35 -04:00
m68k meson: target 2020-08-21 06:30:35 -04:00
microblaze meson: target 2020-08-21 06:30:35 -04:00
mips meson: target 2020-08-21 06:30:35 -04:00
moxie meson: target 2020-08-21 06:30:35 -04:00
nios2 meson: target 2020-08-21 06:30:35 -04:00
openrisc meson: target 2020-08-21 06:30:35 -04:00
ppc meson: target 2020-08-21 06:30:35 -04:00
riscv target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
rx meson: target 2020-08-21 06:30:35 -04:00
s390x target/s390x: fix meson.build issue 2020-08-21 11:55:13 -04:00
sh4 meson: target 2020-08-21 06:30:35 -04:00
sparc meson: target 2020-08-21 06:30:35 -04:00
tilegx meson: target 2020-08-21 06:30:35 -04:00
tricore meson: target 2020-08-21 06:30:35 -04:00
unicore32 meson: target 2020-08-21 06:30:35 -04:00
xtensa meson: target 2020-08-21 06:30:35 -04:00
meson.build meson: target 2020-08-21 06:30:35 -04:00