381 lines
9.6 KiB
C
381 lines
9.6 KiB
C
/*
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* QEMU GRLIB IRQMP Emulator
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*
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* (Multiprocessor and extended interrupt not supported)
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*
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* Copyright (c) 2010-2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "cpu.h"
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#include "hw/sparc/grlib.h"
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#include "trace.h"
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#include "qapi/error.h"
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#define IRQMP_MAX_CPU 16
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#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
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/* Memory mapped register offsets */
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#define LEVEL_OFFSET 0x00
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#define PENDING_OFFSET 0x04
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#define FORCE0_OFFSET 0x08
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#define CLEAR_OFFSET 0x0C
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#define MP_STATUS_OFFSET 0x10
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#define BROADCAST_OFFSET 0x14
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#define MASK_OFFSET 0x40
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#define FORCE_OFFSET 0x80
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#define EXTENDED_OFFSET 0xC0
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#define TYPE_GRLIB_IRQMP "grlib,irqmp"
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#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
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typedef struct IRQMPState IRQMPState;
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typedef struct IRQMP {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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void *set_pil_in;
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void *set_pil_in_opaque;
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IRQMPState *state;
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} IRQMP;
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struct IRQMPState {
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uint32_t level;
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uint32_t pending;
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uint32_t clear;
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uint32_t broadcast;
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uint32_t mask[IRQMP_MAX_CPU];
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uint32_t force[IRQMP_MAX_CPU];
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uint32_t extended[IRQMP_MAX_CPU];
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IRQMP *parent;
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};
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static void grlib_irqmp_check_irqs(IRQMPState *state)
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{
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uint32_t pend = 0;
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uint32_t level0 = 0;
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uint32_t level1 = 0;
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set_pil_in_fn set_pil_in;
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assert(state != NULL);
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assert(state->parent != NULL);
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/* IRQ for CPU 0 (no SMP support) */
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pend = (state->pending | state->force[0])
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& state->mask[0];
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level0 = pend & ~state->level;
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level1 = pend & state->level;
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trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
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state->mask[0], level1, level0);
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set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
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/* Trigger level1 interrupt first and level0 if there is no level1 */
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if (level1 != 0) {
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set_pil_in(state->parent->set_pil_in_opaque, level1);
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} else {
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set_pil_in(state->parent->set_pil_in_opaque, level0);
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}
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}
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void grlib_irqmp_ack(DeviceState *dev, int intno)
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{
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IRQMP *irqmp = GRLIB_IRQMP(dev);
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IRQMPState *state;
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uint32_t mask;
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state = irqmp->state;
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assert(state != NULL);
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intno &= 15;
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mask = 1 << intno;
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trace_grlib_irqmp_ack(intno);
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/* Clear registers */
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state->pending &= ~mask;
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state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
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grlib_irqmp_check_irqs(state);
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}
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void grlib_irqmp_set_irq(void *opaque, int irq, int level)
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{
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IRQMP *irqmp = GRLIB_IRQMP(opaque);
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IRQMPState *s;
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int i = 0;
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s = irqmp->state;
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assert(s != NULL);
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assert(s->parent != NULL);
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if (level) {
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trace_grlib_irqmp_set_irq(irq);
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if (s->broadcast & 1 << irq) {
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/* Broadcasted IRQ */
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for (i = 0; i < IRQMP_MAX_CPU; i++) {
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s->force[i] |= 1 << irq;
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}
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} else {
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s->pending |= 1 << irq;
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}
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grlib_irqmp_check_irqs(s);
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}
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}
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static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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IRQMP *irqmp = opaque;
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IRQMPState *state;
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assert(irqmp != NULL);
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state = irqmp->state;
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assert(state != NULL);
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addr &= 0xff;
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/* global registers */
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switch (addr) {
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case LEVEL_OFFSET:
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return state->level;
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case PENDING_OFFSET:
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return state->pending;
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case FORCE0_OFFSET:
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/* This register is an "alias" for the force register of CPU 0 */
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return state->force[0];
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case CLEAR_OFFSET:
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case MP_STATUS_OFFSET:
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/* Always read as 0 */
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return 0;
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case BROADCAST_OFFSET:
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return state->broadcast;
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default:
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break;
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}
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/* mask registers */
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if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
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int cpu = (addr - MASK_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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return state->mask[cpu];
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}
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/* force registers */
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if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
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int cpu = (addr - FORCE_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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return state->force[cpu];
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}
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/* extended (not supported) */
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if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
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int cpu = (addr - EXTENDED_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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return state->extended[cpu];
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}
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trace_grlib_irqmp_readl_unknown(addr);
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return 0;
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}
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static void grlib_irqmp_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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IRQMP *irqmp = opaque;
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IRQMPState *state;
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assert(irqmp != NULL);
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state = irqmp->state;
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assert(state != NULL);
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addr &= 0xff;
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/* global registers */
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switch (addr) {
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case LEVEL_OFFSET:
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value &= 0xFFFF << 1; /* clean up the value */
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state->level = value;
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return;
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case PENDING_OFFSET:
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/* Read Only */
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return;
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case FORCE0_OFFSET:
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/* This register is an "alias" for the force register of CPU 0 */
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value &= 0xFFFE; /* clean up the value */
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state->force[0] = value;
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grlib_irqmp_check_irqs(irqmp->state);
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return;
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case CLEAR_OFFSET:
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value &= ~1; /* clean up the value */
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state->pending &= ~value;
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return;
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case MP_STATUS_OFFSET:
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/* Read Only (no SMP support) */
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return;
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case BROADCAST_OFFSET:
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value &= 0xFFFE; /* clean up the value */
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state->broadcast = value;
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return;
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default:
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break;
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}
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/* mask registers */
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if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
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int cpu = (addr - MASK_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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value &= ~1; /* clean up the value */
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state->mask[cpu] = value;
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grlib_irqmp_check_irqs(irqmp->state);
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return;
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}
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/* force registers */
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if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
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int cpu = (addr - FORCE_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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uint32_t force = value & 0xFFFE;
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uint32_t clear = (value >> 16) & 0xFFFE;
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uint32_t old = state->force[cpu];
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state->force[cpu] = (old | force) & ~clear;
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grlib_irqmp_check_irqs(irqmp->state);
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return;
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}
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/* extended (not supported) */
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if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
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int cpu = (addr - EXTENDED_OFFSET) / 4;
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assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
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value &= 0xF; /* clean up the value */
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state->extended[cpu] = value;
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return;
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}
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trace_grlib_irqmp_writel_unknown(addr, value);
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}
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static const MemoryRegionOps grlib_irqmp_ops = {
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.read = grlib_irqmp_read,
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.write = grlib_irqmp_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void grlib_irqmp_reset(DeviceState *d)
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{
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IRQMP *irqmp = GRLIB_IRQMP(d);
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assert(irqmp->state != NULL);
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memset(irqmp->state, 0, sizeof *irqmp->state);
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irqmp->state->parent = irqmp;
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}
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static void grlib_irqmp_init(Object *obj)
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{
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IRQMP *irqmp = GRLIB_IRQMP(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
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"irqmp", IRQMP_REG_SIZE);
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irqmp->state = g_malloc0(sizeof *irqmp->state);
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sysbus_init_mmio(dev, &irqmp->iomem);
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}
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static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
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{
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IRQMP *irqmp = GRLIB_IRQMP(dev);
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/* Check parameters */
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if (irqmp->set_pil_in == NULL) {
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error_setg(errp, "set_pil_in cannot be NULL.");
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}
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}
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static Property grlib_irqmp_properties[] = {
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DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
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DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = grlib_irqmp_reset;
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dc->props = grlib_irqmp_properties;
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/* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
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dc->user_creatable = false;
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dc->realize = grlib_irqmp_realize;
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}
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static const TypeInfo grlib_irqmp_info = {
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.name = TYPE_GRLIB_IRQMP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IRQMP),
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.instance_init = grlib_irqmp_init,
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.class_init = grlib_irqmp_class_init,
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};
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static void grlib_irqmp_register_types(void)
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{
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type_register_static(&grlib_irqmp_info);
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}
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type_init(grlib_irqmp_register_types)
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