329 lines
10 KiB
C
329 lines
10 KiB
C
/*
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* Xilinx PCIe host controller emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci-host/xilinx-pcie.h"
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enum root_cfg_reg {
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/* Interrupt Decode Register */
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ROOTCFG_INTDEC = 0x138,
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/* Interrupt Mask Register */
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ROOTCFG_INTMASK = 0x13c,
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/* INTx Interrupt Received */
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#define ROOTCFG_INTMASK_INTX (1 << 16)
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/* MSI Interrupt Received */
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#define ROOTCFG_INTMASK_MSI (1 << 17)
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/* PHY Status/Control Register */
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ROOTCFG_PSCR = 0x144,
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/* Link Up */
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#define ROOTCFG_PSCR_LINK_UP (1 << 11)
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/* Root Port Status/Control Register */
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ROOTCFG_RPSCR = 0x148,
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/* Bridge Enable */
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#define ROOTCFG_RPSCR_BRIDGEEN (1 << 0)
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/* Interrupt FIFO Not Empty */
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#define ROOTCFG_RPSCR_INTNEMPTY (1 << 18)
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/* Interrupt FIFO Overflow */
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#define ROOTCFG_RPSCR_INTOVF (1 << 19)
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/* Root Port Interrupt FIFO Read Register 1 */
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ROOTCFG_RPIFR1 = 0x158,
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#define ROOTCFG_RPIFR1_INT_LANE_SHIFT 27
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#define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29
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#define ROOTCFG_RPIFR1_INT_VALID_SHIFT 31
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/* Root Port Interrupt FIFO Read Register 2 */
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ROOTCFG_RPIFR2 = 0x15c,
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};
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static void xilinx_pcie_update_intr(XilinxPCIEHost *s,
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uint32_t set, uint32_t clear)
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{
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int level;
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s->intr |= set;
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s->intr &= ~clear;
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if (s->intr_fifo_r != s->intr_fifo_w) {
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s->intr |= ROOTCFG_INTMASK_INTX;
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}
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level = !!(s->intr & s->intr_mask);
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qemu_set_irq(s->irq, level);
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}
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static void xilinx_pcie_queue_intr(XilinxPCIEHost *s,
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uint32_t fifo_reg1, uint32_t fifo_reg2)
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{
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XilinxPCIEInt *intr;
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unsigned int new_w;
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new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo);
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if (new_w == s->intr_fifo_r) {
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s->rpscr |= ROOTCFG_RPSCR_INTOVF;
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return;
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}
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intr = &s->intr_fifo[s->intr_fifo_w];
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s->intr_fifo_w = new_w;
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intr->fifo_reg1 = fifo_reg1;
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intr->fifo_reg2 = fifo_reg2;
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xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0);
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}
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static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level)
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{
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XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque);
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xilinx_pcie_queue_intr(s,
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(irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) |
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(level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) |
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(1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT),
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0);
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}
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static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
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snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);
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/* PCI configuration space */
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pcie_host_mmcfg_init(pex, s->cfg_size);
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/* MMIO region */
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memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
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memory_region_set_enabled(&s->mmio, false);
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/* dummy I/O region */
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memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);
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memory_region_set_enabled(&s->io, false);
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/* interrupt out */
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qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
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sysbus_init_mmio(sbd, &pex->mmio);
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sysbus_init_mmio(sbd, &s->mmio);
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pci->bus = pci_register_bus(dev, s->name, xilinx_pcie_set_irq,
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pci_swizzle_map_irq_fn, s, &s->mmio,
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&s->io, 0, 4, TYPE_PCIE_BUS);
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qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
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qdev_init_nofail(DEVICE(&s->root));
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}
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static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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return "0000:00";
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}
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static void xilinx_pcie_host_init(Object *obj)
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{
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XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
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XilinxPCIERoot *root = &s->root;
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object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT);
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object_property_add_child(obj, "root", OBJECT(root), NULL);
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qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
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qdev_prop_set_bit(DEVICE(root), "multifunction", false);
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}
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static Property xilinx_pcie_host_props[] = {
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DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
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DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
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DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 << 20),
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DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
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DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 << 20),
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DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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hc->root_bus_path = xilinx_pcie_host_root_bus_path;
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dc->realize = xilinx_pcie_host_realize;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->fw_name = "pci";
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dc->props = xilinx_pcie_host_props;
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}
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static const TypeInfo xilinx_pcie_host_info = {
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.name = TYPE_XILINX_PCIE_HOST,
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.parent = TYPE_PCIE_HOST_BRIDGE,
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.instance_size = sizeof(XilinxPCIEHost),
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.instance_init = xilinx_pcie_host_init,
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.class_init = xilinx_pcie_host_class_init,
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};
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static uint32_t xilinx_pcie_root_config_read(PCIDevice *d,
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uint32_t address, int len)
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{
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XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
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uint32_t val;
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switch (address) {
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case ROOTCFG_INTDEC:
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val = s->intr;
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break;
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case ROOTCFG_INTMASK:
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val = s->intr_mask;
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break;
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case ROOTCFG_PSCR:
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val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0;
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break;
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case ROOTCFG_RPSCR:
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if (s->intr_fifo_r != s->intr_fifo_w) {
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s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY;
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} else {
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s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY;
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}
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val = s->rpscr;
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break;
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case ROOTCFG_RPIFR1:
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if (s->intr_fifo_w == s->intr_fifo_r) {
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/* FIFO empty */
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val = 0;
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} else {
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val = s->intr_fifo[s->intr_fifo_r].fifo_reg1;
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}
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break;
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case ROOTCFG_RPIFR2:
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if (s->intr_fifo_w == s->intr_fifo_r) {
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/* FIFO empty */
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val = 0;
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} else {
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val = s->intr_fifo[s->intr_fifo_r].fifo_reg2;
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}
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break;
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default:
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val = pci_default_read_config(d, address, len);
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break;
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}
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return val;
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}
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static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
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switch (address) {
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case ROOTCFG_INTDEC:
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xilinx_pcie_update_intr(s, 0, val);
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break;
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case ROOTCFG_INTMASK:
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s->intr_mask = val;
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xilinx_pcie_update_intr(s, 0, 0);
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break;
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case ROOTCFG_RPSCR:
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s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN;
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s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN;
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memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN);
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if (val & ROOTCFG_INTMASK_INTX) {
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s->rpscr &= ~ROOTCFG_INTMASK_INTX;
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}
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break;
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case ROOTCFG_RPIFR1:
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case ROOTCFG_RPIFR2:
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if (s->intr_fifo_w == s->intr_fifo_r) {
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/* FIFO empty */
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return;
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} else {
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s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo);
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}
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break;
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default:
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pci_default_write_config(d, address, val, len);
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break;
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}
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}
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static int xilinx_pcie_root_init(PCIDevice *dev)
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{
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BusState *bus = qdev_get_parent_bus(DEVICE(dev));
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XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);
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pci_set_word(dev->config + PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pci_set_word(dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
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pci_set_word(dev->config + PCI_MEMORY_LIMIT,
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((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0);
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pci_bridge_initfn(dev, TYPE_PCI_BUS);
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if (pcie_endpoint_cap_v1_init(dev, 0x80) < 0) {
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hw_error("Failed to initialize PCIe capability");
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}
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return 0;
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}
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static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->desc = "Xilinx AXI-PCIe Host Bridge";
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k->vendor_id = PCI_VENDOR_ID_XILINX;
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k->device_id = 0x7021;
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k->revision = 0;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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k->is_express = true;
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k->is_bridge = true;
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k->init = xilinx_pcie_root_init;
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k->exit = pci_bridge_exitfn;
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dc->reset = pci_bridge_reset;
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k->config_read = xilinx_pcie_root_config_read;
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k->config_write = xilinx_pcie_root_config_write;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo xilinx_pcie_root_info = {
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.name = TYPE_XILINX_PCIE_ROOT,
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.parent = TYPE_PCI_BRIDGE,
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.instance_size = sizeof(XilinxPCIERoot),
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.class_init = xilinx_pcie_root_class_init,
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};
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static void xilinx_pcie_register(void)
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{
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type_register_static(&xilinx_pcie_root_info);
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type_register_static(&xilinx_pcie_host_info);
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}
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type_init(xilinx_pcie_register)
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