276 lines
8.3 KiB
C
276 lines
8.3 KiB
C
/*
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* QEMU PowerPC PowerNV XSCOM bus
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "qemu/log.h"
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#include "sysemu/hw_accel.h"
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#include "target/ppc/cpu.h"
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#include "hw/sysbus.h"
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#include "hw/ppc/fdt.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include <libfdt.h>
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static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
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{
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/*
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* TODO: When the read/write comes from the monitor, NULL is
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* passed for the cpu, and no CPU completion is generated.
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*/
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if (cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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/*
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* TODO: Need a CPU helper to set HMER, also handle generation
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* of HMIs
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*/
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cpu_synchronize_state(cs);
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env->spr[SPR_HMER] |= hmer_bits;
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}
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}
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static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
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addr &= (PNV_XSCOM_SIZE - 1);
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if (pcc->chip_type == PNV_CHIP_POWER9) {
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return addr >> 3;
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} else {
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return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
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}
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}
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static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
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{
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switch (pcba) {
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case 0xf000f:
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return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
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case 0x1010c00: /* PIBAM FIR */
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case 0x1010c03: /* PIBAM FIR MASK */
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case 0x2020007: /* ADU stuff */
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case 0x2020009: /* ADU stuff */
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case 0x202000f: /* ADU stuff */
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return 0;
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case 0x2013f00: /* PBA stuff */
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case 0x2013f01: /* PBA stuff */
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case 0x2013f02: /* PBA stuff */
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case 0x2013f03: /* PBA stuff */
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case 0x2013f04: /* PBA stuff */
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case 0x2013f05: /* PBA stuff */
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case 0x2013f06: /* PBA stuff */
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case 0x2013f07: /* PBA stuff */
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return 0;
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case 0x2013028: /* CAPP stuff */
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case 0x201302a: /* CAPP stuff */
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case 0x2013801: /* CAPP stuff */
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case 0x2013802: /* CAPP stuff */
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return 0;
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default:
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return -1;
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}
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}
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static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
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{
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/* We ignore writes to these */
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switch (pcba) {
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case 0xf000f: /* chip id is RO */
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case 0x1010c00: /* PIBAM FIR */
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case 0x1010c01: /* PIBAM FIR */
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case 0x1010c02: /* PIBAM FIR */
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case 0x1010c03: /* PIBAM FIR MASK */
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case 0x1010c04: /* PIBAM FIR MASK */
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case 0x1010c05: /* PIBAM FIR MASK */
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case 0x2020007: /* ADU stuff */
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case 0x2020009: /* ADU stuff */
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case 0x202000f: /* ADU stuff */
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return true;
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default:
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return false;
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}
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}
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static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
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{
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PnvChip *chip = opaque;
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uint32_t pcba = pnv_xscom_pcba(chip, addr);
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uint64_t val = 0;
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MemTxResult result;
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/* Handle some SCOMs here before dispatch */
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val = xscom_read_default(chip, pcba);
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if (val != -1) {
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goto complete;
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}
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val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
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HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
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xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
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return 0;
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}
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complete:
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xscom_complete(current_cpu, HMER_XSCOM_DONE);
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return val;
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}
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static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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PnvChip *chip = opaque;
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uint32_t pcba = pnv_xscom_pcba(chip, addr);
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MemTxResult result;
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/* Handle some SCOMs here before dispatch */
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if (xscom_write_default(chip, pcba, val)) {
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goto complete;
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}
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address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
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HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
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addr, pcba, val);
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xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
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return;
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}
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complete:
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xscom_complete(current_cpu, HMER_XSCOM_DONE);
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}
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const MemoryRegionOps pnv_xscom_ops = {
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.read = xscom_read,
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.write = xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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void pnv_xscom_realize(PnvChip *chip, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
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char *name;
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name = g_strdup_printf("xscom-%x", chip->chip_id);
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memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
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chip, name, PNV_XSCOM_SIZE);
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sysbus_init_mmio(sbd, &chip->xscom_mmio);
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memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE);
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address_space_init(&chip->xscom_as, &chip->xscom, name);
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g_free(name);
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}
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static const TypeInfo pnv_xscom_interface_info = {
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.name = TYPE_PNV_XSCOM_INTERFACE,
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.parent = TYPE_INTERFACE,
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.class_size = sizeof(PnvXScomInterfaceClass),
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};
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static void pnv_xscom_register_types(void)
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{
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type_register_static(&pnv_xscom_interface_info);
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}
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type_init(pnv_xscom_register_types)
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typedef struct ForeachPopulateArgs {
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void *fdt;
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int xscom_offset;
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} ForeachPopulateArgs;
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static int xscom_populate_child(Object *child, void *opaque)
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{
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if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
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ForeachPopulateArgs *args = opaque;
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PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
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PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
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if (xc->populate) {
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_FDT((xc->populate(xd, args->fdt, args->xscom_offset)));
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}
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}
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return 0;
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}
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static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
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static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
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int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset)
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{
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uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)),
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cpu_to_be64(PNV_XSCOM_SIZE) };
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int xscom_offset;
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ForeachPopulateArgs args;
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char *name;
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
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name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
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xscom_offset = fdt_add_subnode(fdt, root_offset, name);
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_FDT(xscom_offset);
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g_free(name);
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_FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
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_FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
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_FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
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_FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
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if (pcc->chip_type == PNV_CHIP_POWER9) {
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_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
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sizeof(compat_p9))));
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} else {
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_FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
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sizeof(compat_p8))));
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}
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_FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
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args.fdt = fdt;
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args.xscom_offset = xscom_offset;
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object_child_foreach(OBJECT(chip), xscom_populate_child, &args);
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return 0;
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}
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void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
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{
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memory_region_add_subregion(&chip->xscom, offset << 3, mr);
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}
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void pnv_xscom_region_init(MemoryRegion *mr,
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struct Object *owner,
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const MemoryRegionOps *ops,
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void *opaque,
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const char *name,
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uint64_t size)
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{
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memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
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}
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