609 lines
15 KiB
C
609 lines
15 KiB
C
/*
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* QEMU JAZZ RC4030 chipset
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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//#define DEBUG_RC4030
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#ifdef DEBUG_RC4030
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static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
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"network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
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#endif
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typedef struct rc4030State
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{
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uint32_t config; /* 0x0000: RC4030 config register */
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uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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/* DMA */
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uint32_t dma_regs[8][4];
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uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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/* cache */
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uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
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uint32_t offset208;
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uint32_t offset210;
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uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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uint32_t offset238;
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uint32_t rem_speed[15];
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uint32_t imr_jazz; /* Local bus int enable mask */
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uint32_t isr_jazz; /* Local bus int source */
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/* timer */
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QEMUTimer *periodic_timer;
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uint32_t itr; /* Interval timer reload */
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uint32_t dummy32;
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qemu_irq timer_irq;
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qemu_irq jazz_bus_irq;
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} rc4030State;
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static void set_next_tick(rc4030State *s)
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{
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qemu_irq_lower(s->timer_irq);
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uint32_t hz;
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hz = 1000 / (s->itr + 1);
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qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / hz);
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}
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/* called for accesses to rc4030 */
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static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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{
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rc4030State *s = opaque;
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uint32_t val;
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addr &= 0x3fff;
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switch (addr & ~0x3) {
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/* Global config register */
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case 0x0000:
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val = s->config;
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break;
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/* Invalid Address register */
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case 0x0010:
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val = s->invalid_address_register;
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break;
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/* DMA transl. table base */
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case 0x0018:
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val = s->dma_tl_base;
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break;
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/* DMA transl. table limit */
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case 0x0020:
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val = s->dma_tl_limit;
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break;
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/* Remote Failed Address */
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case 0x0038:
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val = s->remote_failed_address;
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break;
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/* Memory Failed Address */
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case 0x0040:
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val = s->memory_failed_address;
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break;
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/* I/O Cache Byte Mask */
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case 0x0058:
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val = s->cache_bmask;
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/* HACK */
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if (s->cache_bmask == (uint32_t)-1)
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s->cache_bmask = 0;
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break;
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/* Remote Speed Registers */
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case 0x0070:
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case 0x0078:
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case 0x0080:
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case 0x0088:
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case 0x0090:
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case 0x0098:
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case 0x00a0:
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case 0x00a8:
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case 0x00b0:
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case 0x00b8:
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case 0x00c0:
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case 0x00c8:
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case 0x00d0:
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case 0x00d8:
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case 0x00e0:
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val = s->rem_speed[(addr - 0x0070) >> 3];
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break;
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/* DMA channel base address */
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case 0x0100:
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case 0x0108:
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case 0x0110:
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case 0x0118:
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case 0x0120:
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case 0x0128:
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case 0x0130:
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case 0x0138:
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case 0x0140:
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case 0x0148:
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case 0x0150:
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case 0x0158:
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case 0x0160:
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case 0x0168:
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case 0x0170:
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case 0x0178:
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case 0x0180:
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case 0x0188:
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case 0x0190:
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case 0x0198:
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case 0x01a0:
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case 0x01a8:
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case 0x01b0:
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case 0x01b8:
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case 0x01c0:
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case 0x01c8:
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case 0x01d0:
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case 0x01d8:
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case 0x01e0:
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case 0x1e8:
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case 0x01f0:
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case 0x01f8:
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{
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int entry = (addr - 0x0100) >> 5;
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int idx = (addr & 0x1f) >> 3;
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val = s->dma_regs[entry][idx];
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}
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break;
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/* Offset 0x0208 */
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case 0x0208:
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val = s->offset208;
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break;
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/* Offset 0x0210 */
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case 0x0210:
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val = s->offset210;
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break;
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/* NV ram protect register */
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case 0x0220:
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val = s->nvram_protect;
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break;
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/* Interval timer count */
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case 0x0230:
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val = s->dummy32;
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qemu_irq_lower(s->timer_irq);
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break;
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/* Offset 0x0238 */
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case 0x0238:
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val = s->offset238;
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr);
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#endif
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val = 0;
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break;
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}
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#ifdef DEBUG_RC4030
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if ((addr & ~3) != 0x230)
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printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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return val;
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}
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static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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if (addr & 0x2)
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return v >> 16;
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else
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return v & 0xffff;
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}
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static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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return (v >> (8 * (addr & 0x3))) & 0xff;
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}
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static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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rc4030State *s = opaque;
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addr &= 0x3fff;
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#ifdef DEBUG_RC4030
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printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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switch (addr & ~0x3) {
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/* Global config register */
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case 0x0000:
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s->config = val;
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break;
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/* DMA transl. table base */
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case 0x0018:
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s->dma_tl_base = val;
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break;
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/* DMA transl. table limit */
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case 0x0020:
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s->dma_tl_limit = val;
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break;
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/* I/O Cache Physical Tag */
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case 0x0048:
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s->cache_ptag = val;
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break;
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/* I/O Cache Logical Tag */
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case 0x0050:
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s->cache_ltag = val;
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break;
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/* I/O Cache Byte Mask */
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case 0x0058:
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s->cache_bmask |= val; /* HACK */
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break;
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/* I/O Cache Buffer Window */
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case 0x0060:
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s->cache_bwin = val;
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/* HACK */
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if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
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target_phys_addr_t dests[] = { 4, 0, 8, 0x10 };
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static int current = 0;
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target_phys_addr_t dest = 0 + dests[current];
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uint8_t buf;
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current = (current + 1) % (sizeof(dests)/sizeof(dests[0]));
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buf = s->cache_bwin - 1;
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cpu_physical_memory_rw(dest, &buf, 1, 1);
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}
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break;
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/* Remote Speed Registers */
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case 0x0070:
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case 0x0078:
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case 0x0080:
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case 0x0088:
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case 0x0090:
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case 0x0098:
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case 0x00a0:
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case 0x00a8:
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case 0x00b0:
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case 0x00b8:
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case 0x00c0:
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case 0x00c8:
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case 0x00d0:
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case 0x00d8:
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case 0x00e0:
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s->rem_speed[(addr - 0x0070) >> 3] = val;
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break;
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/* DMA channel base address */
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case 0x0100:
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case 0x0108:
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case 0x0110:
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case 0x0118:
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case 0x0120:
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case 0x0128:
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case 0x0130:
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case 0x0138:
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case 0x0140:
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case 0x0148:
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case 0x0150:
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case 0x0158:
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case 0x0160:
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case 0x0168:
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case 0x0170:
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case 0x0178:
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case 0x0180:
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case 0x0188:
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case 0x0190:
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case 0x0198:
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case 0x01a0:
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case 0x01a8:
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case 0x01b0:
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case 0x01b8:
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case 0x01c0:
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case 0x01c8:
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case 0x01d0:
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case 0x01d8:
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case 0x01e0:
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case 0x1e8:
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case 0x01f0:
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case 0x01f8:
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{
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int entry = (addr - 0x0100) >> 5;
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int idx = (addr & 0x1f) >> 3;
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s->dma_regs[entry][idx] = val;
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}
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break;
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/* Offset 0x0210 */
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case 0x0210:
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s->offset210 = val;
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break;
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/* Interval timer reload */
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case 0x0228:
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s->itr = val;
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qemu_irq_lower(s->timer_irq);
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set_next_tick(s);
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
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#endif
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break;
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}
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}
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static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
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if (addr & 0x2)
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val = (val << 16) | (old_val & 0x0000ffff);
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else
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val = val | (old_val & 0xffff0000);
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rc4030_writel(opaque, addr & ~0x3, val);
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}
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static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
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switch (addr & 3) {
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case 0:
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val = val | (old_val & 0xffffff00);
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break;
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case 1:
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val = (val << 8) | (old_val & 0xffff00ff);
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break;
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case 2:
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val = (val << 16) | (old_val & 0xff00ffff);
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break;
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case 3:
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val = (val << 24) | (old_val & 0x00ffffff);
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break;
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}
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rc4030_writel(opaque, addr & ~0x3, val);
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}
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static CPUReadMemoryFunc *rc4030_read[3] = {
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rc4030_readb,
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rc4030_readw,
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rc4030_readl,
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};
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static CPUWriteMemoryFunc *rc4030_write[3] = {
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rc4030_writeb,
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rc4030_writew,
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rc4030_writel,
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};
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static void update_jazz_irq(rc4030State *s)
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{
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uint16_t pending;
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pending = s->isr_jazz & s->imr_jazz;
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#ifdef DEBUG_RC4030
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if (s->isr_jazz != 0) {
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uint32_t irq = 0;
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printf("jazz pending:");
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for (irq = 0; irq < sizeof(irq_names)/sizeof(irq_names[0]); irq++) {
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if (s->isr_jazz & (1 << irq)) {
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printf(" %s", irq_names[irq]);
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if (!(s->imr_jazz & (1 << irq))) {
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printf("(ignored)");
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}
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}
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}
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printf("\n");
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}
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#endif
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if (pending != 0)
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qemu_irq_raise(s->jazz_bus_irq);
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else
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qemu_irq_lower(s->jazz_bus_irq);
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}
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static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
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{
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rc4030State *s = opaque;
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if (level) {
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s->isr_jazz |= 1 << irq;
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} else {
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s->isr_jazz &= ~(1 << irq);
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}
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update_jazz_irq(s);
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}
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static void rc4030_periodic_timer(void *opaque)
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{
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rc4030State *s = opaque;
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set_next_tick(s);
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qemu_irq_raise(s->timer_irq);
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}
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static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
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{
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rc4030State *s = opaque;
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uint32_t val;
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uint32_t irq;
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addr &= 0xfff;
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switch (addr) {
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case 0x00: {
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/* Local bus int source */
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uint32_t pending = s->isr_jazz & s->imr_jazz;
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val = 0;
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irq = 0;
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while (pending) {
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if (pending & 1) {
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//printf("returning irq %s\n", irq_names[irq]);
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val = (irq + 1) << 2;
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break;
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}
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irq++;
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pending >>= 1;
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}
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break;
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}
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr);
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#endif
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val = 0;
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}
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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return val;
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}
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static uint32_t int_readw(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = int_readb(opaque, addr);
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v |= int_readb(opaque, addr + 1) << 8;
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return v;
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}
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static uint32_t int_readl(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v;
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v = int_readb(opaque, addr);
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v |= int_readb(opaque, addr + 1) << 8;
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v |= int_readb(opaque, addr + 2) << 16;
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v |= int_readb(opaque, addr + 3) << 24;
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return v;
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}
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static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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rc4030State *s = opaque;
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addr &= 0xfff;
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
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#endif
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switch (addr) {
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/* Local bus int enable mask */
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case 0x02:
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s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s);
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break;
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case 0x03:
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s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s);
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break;
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default:
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#ifdef DEBUG_RC4030
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printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
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#endif
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break;
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}
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}
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static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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int_writeb(opaque, addr, val & 0xff);
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int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
|
}
|
|
|
|
static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
int_writeb(opaque, addr, val & 0xff);
|
|
int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
|
int_writeb(opaque, addr + 2, (val >> 16) & 0xff);
|
|
int_writeb(opaque, addr + 3, (val >> 24) & 0xff);
|
|
}
|
|
|
|
static CPUReadMemoryFunc *int_read[3] = {
|
|
int_readb,
|
|
int_readw,
|
|
int_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc *int_write[3] = {
|
|
int_writeb,
|
|
int_writew,
|
|
int_writel,
|
|
};
|
|
|
|
#define G364_512KB_RAM (0x0)
|
|
#define G364_2MB_RAM (0x1)
|
|
#define G364_8MB_RAM (0x2)
|
|
#define G364_32MB_RAM (0x3)
|
|
|
|
static void rc4030_reset(void *opaque)
|
|
{
|
|
rc4030State *s = opaque;
|
|
int i;
|
|
|
|
s->config = (G364_2MB_RAM << 8) | 0x04;
|
|
s->invalid_address_register = 0;
|
|
|
|
memset(s->dma_regs, 0, sizeof(s->dma_regs));
|
|
s->dma_tl_base = s->dma_tl_limit = 0;
|
|
|
|
s->remote_failed_address = s->memory_failed_address = 0;
|
|
s->cache_ptag = s->cache_ltag = 0;
|
|
s->cache_bmask = s->cache_bwin = 0;
|
|
|
|
s->offset208 = 0;
|
|
s->offset210 = 0x18186;
|
|
s->nvram_protect = 7;
|
|
s->offset238 = 7;
|
|
for (i = 0; i < 15; i++)
|
|
s->rem_speed[i] = 7;
|
|
s->imr_jazz = s->isr_jazz = 0;
|
|
|
|
s->itr = 0;
|
|
s->dummy32 = 0;
|
|
|
|
qemu_irq_lower(s->timer_irq);
|
|
qemu_irq_lower(s->jazz_bus_irq);
|
|
}
|
|
|
|
qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
|
|
{
|
|
rc4030State *s;
|
|
int s_chipset, s_int;
|
|
|
|
s = qemu_mallocz(sizeof(rc4030State));
|
|
if (!s)
|
|
return NULL;
|
|
|
|
s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
|
|
s->timer_irq = timer;
|
|
s->jazz_bus_irq = jazz_bus;
|
|
|
|
qemu_register_reset(rc4030_reset, s);
|
|
rc4030_reset(s);
|
|
|
|
s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
|
|
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
|
|
s_int = cpu_register_io_memory(0, int_read, int_write, s);
|
|
cpu_register_physical_memory(0xf0000000, 0x00001000, s_int);
|
|
|
|
return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
|
}
|