Keith Packard a10b9d93ec riscv: Add semihosting support ... Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>		2021-01-18 10:05:06 +00:00
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alpha
arm	semihosting: Change common-semi API to be architecture-independent	2021-01-18 10:05:06 +00:00
avr
cris
hppa
i386	target/i386: Use X86Seg enum for segment registers	2021-01-12 17:05:10 +01:00
lm32
m68k	gdbstub: drop CPUEnv from gdb_exit()	2021-01-18 10:05:06 +00:00
microblaze
mips	target/mips: Remove vendor specific CPU definitions	2021-01-14 17:13:54 +01:00
moxie
nios2	gdbstub: drop CPUEnv from gdb_exit()	2021-01-18 10:05:06 +00:00
openrisc
ppc
riscv	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
rx
s390x
sh4
sparc
tilegx
tricore
unicore32
xtensa
meson.build