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qemu-e2k/linux-user/riscv
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Richard Henderson 07a6ecf48f linux-user: Introduce cpu_clone_regs_parent 
We will need a target-specific hook for adjusting registers
in the parent during clone.  Add an empty inline function for
each target, and invoke it from the proper places.

Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191106113318.10226-11-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
 		2019-11-06 13:43:25 +01:00
..
cpu_loop.c linux-user/riscv: Propagate fault address 2019-10-28 07:47:27 -07:00
signal.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
sockbits.h linux-user: move socket.h generic definitions to generic/sockbits.h 2018-05-25 10:10:55 +02:00
syscall_nr.h RISC-V: Update syscall list for 32-bit support. 2019-06-25 22:37:08 -07:00
target_cpu.h linux-user: Introduce cpu_clone_regs_parent 2019-11-06 13:43:25 +01:00
target_elf.h linux-user/riscv: Add the CPU type as a comment 2019-05-24 12:09:23 -07:00
target_fcntl.h linux-user: move generic fcntl definitions to generic/fcntl.h 2018-06-04 01:30:43 +02:00
target_signal.h linux-user/nios2 linux-user/riscv: Clean up header guards 2019-05-13 08:58:55 +02:00
target_structs.h linux-user/nios2 linux-user/riscv: Clean up header guards 2019-05-13 08:58:55 +02:00
target_syscall.h Supply missing header guards 2019-06-12 13:20:21 +02:00
termbits.h Supply missing header guards 2019-06-12 13:20:21 +02:00