9547754f40
Inject poison using QMP command cxl-inject-poison to add an entry to the poison list. For now, the poison is not returned CXL.mem reads, but only via the mailbox command Get Poison List. So a normal memory read to an address that is on the poison list will not yet result in a synchronous exception (and similar for partial cacheline writes). That is left for a future patch. See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h) Kernel patches to use this interface here: https://lore.kernel.org/linux-cxl/cover.1665606782.git.alison.schofield@intel.com/ To inject poison using QMP (telnet to the QMP port) { "execute": "qmp_capabilities" } { "execute": "cxl-inject-poison", "arguments": { "path": "/machine/peripheral/cxl-pmem0", "start": 2048, "length": 256 } } Adjusted to select a device on your machine. Note that the poison list supported is kept short enough to avoid the complexity of state machine that is needed to handle the MORE flag. Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230526170010.574-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
65 lines
1.4 KiB
C
65 lines
1.4 KiB
C
/*
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* QEMU CXL Support
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*
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* Copyright (c) 2020 Intel
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef CXL_H
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#define CXL_H
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#include "qapi/qapi-types-machine.h"
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#include "qapi/qapi-visit-machine.h"
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#include "hw/pci/pci_host.h"
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#include "cxl_pci.h"
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#include "cxl_component.h"
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#include "cxl_device.h"
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#define CXL_CACHE_LINE_SIZE 64
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#define CXL_COMPONENT_REG_BAR_IDX 0
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#define CXL_DEVICE_REG_BAR_IDX 2
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#define CXL_WINDOW_MAX 10
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typedef struct PXBCXLDev PXBCXLDev;
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typedef struct CXLFixedWindow {
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uint64_t size;
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char **targets;
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PXBCXLDev *target_hbs[8];
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uint8_t num_targets;
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uint8_t enc_int_ways;
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uint8_t enc_int_gran;
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/* Todo: XOR based interleaving */
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MemoryRegion mr;
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hwaddr base;
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} CXLFixedWindow;
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typedef struct CXLState {
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bool is_enabled;
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MemoryRegion host_mr;
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unsigned int next_mr_idx;
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GList *fixed_windows;
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CXLFixedMemoryWindowOptionsList *cfmw_list;
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} CXLState;
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struct CXLHost {
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PCIHostState parent_obj;
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CXLComponentState cxl_cstate;
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bool passthrough;
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};
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#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
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OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
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#define TYPE_CXL_USP "cxl-upstream"
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typedef struct CXLUpstreamPort CXLUpstreamPort;
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DECLARE_INSTANCE_CHECKER(CXLUpstreamPort, CXL_USP, TYPE_CXL_USP)
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CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp);
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#endif
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