4a52ef61d9
Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner R40 SDRAM controller. This driver only support 256M, 512M and 1024M memory now. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/*
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* Allwinner R40 SDRAM Controller emulation
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*
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* Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MISC_ALLWINNER_R40_DRAMC_H
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#define HW_MISC_ALLWINNER_R40_DRAMC_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "exec/hwaddr.h"
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/**
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* Constants
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* @{
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*/
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/** Highest register address used by DRAMCOM module */
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#define AW_R40_DRAMCOM_REGS_MAXADDR (0x804)
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/** Total number of known DRAMCOM registers */
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#define AW_R40_DRAMCOM_REGS_NUM (AW_R40_DRAMCOM_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMCTL module */
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#define AW_R40_DRAMCTL_REGS_MAXADDR (0x88c)
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/** Total number of known DRAMCTL registers */
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#define AW_R40_DRAMCTL_REGS_NUM (AW_R40_DRAMCTL_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMPHY module */
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#define AW_R40_DRAMPHY_REGS_MAXADDR (0x4)
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/** Total number of known DRAMPHY registers */
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#define AW_R40_DRAMPHY_REGS_NUM (AW_R40_DRAMPHY_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** @} */
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/**
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* Object model
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* @{
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*/
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#define TYPE_AW_R40_DRAMC "allwinner-r40-dramc"
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OBJECT_DECLARE_SIMPLE_TYPE(AwR40DramCtlState, AW_R40_DRAMC)
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/** @} */
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/**
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* Allwinner R40 SDRAM Controller object instance state.
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*/
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struct AwR40DramCtlState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/** Physical base address for start of RAM */
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hwaddr ram_addr;
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/** Total RAM size in megabytes */
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uint32_t ram_size;
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uint8_t set_row_bits;
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uint8_t set_bank_bits;
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uint8_t set_col_bits;
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/**
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* @name Memory Regions
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* @{
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*/
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MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
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MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
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MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
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MemoryRegion dram_high; /**< The high 1G dram for dualrank detect */
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MemoryRegion detect_cells; /**< DRAM memory cells for auto detect */
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/** @} */
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/**
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* @name Hardware Registers
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* @{
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*/
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uint32_t dramcom[AW_R40_DRAMCOM_REGS_NUM]; /**< DRAMCOM registers */
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uint32_t dramctl[AW_R40_DRAMCTL_REGS_NUM]; /**< DRAMCTL registers */
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uint32_t dramphy[AW_R40_DRAMPHY_REGS_NUM] ;/**< DRAMPHY registers */
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/** @} */
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};
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#endif /* HW_MISC_ALLWINNER_R40_DRAMC_H */
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