4ea2449b58
These instructions are all privileged. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-42-richard.henderson@linaro.org>
494 lines
14 KiB
C
494 lines
14 KiB
C
/*
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* x86 misc helpers - sysemu code
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "exec/address-spaces.h"
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#include "tcg/helper-tcg.h"
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void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
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{
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address_space_stb(&address_space_io, port, data,
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cpu_get_mem_attrs(env), NULL);
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}
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target_ulong helper_inb(CPUX86State *env, uint32_t port)
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{
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return address_space_ldub(&address_space_io, port,
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cpu_get_mem_attrs(env), NULL);
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}
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void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
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{
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address_space_stw(&address_space_io, port, data,
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cpu_get_mem_attrs(env), NULL);
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}
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target_ulong helper_inw(CPUX86State *env, uint32_t port)
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{
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return address_space_lduw(&address_space_io, port,
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cpu_get_mem_attrs(env), NULL);
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}
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void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
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{
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address_space_stl(&address_space_io, port, data,
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cpu_get_mem_attrs(env), NULL);
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}
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target_ulong helper_inl(CPUX86State *env, uint32_t port)
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{
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return address_space_ldl(&address_space_io, port,
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cpu_get_mem_attrs(env), NULL);
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}
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target_ulong helper_read_crN(CPUX86State *env, int reg)
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{
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target_ulong val;
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switch (reg) {
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default:
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val = env->cr[reg];
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break;
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case 8:
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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val = cpu_get_apic_tpr(env_archcpu(env)->apic_state);
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} else {
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val = env->v_tpr;
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}
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break;
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}
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return val;
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}
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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{
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switch (reg) {
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case 0:
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cpu_x86_update_cr0(env, t0);
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break;
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case 3:
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cpu_x86_update_cr3(env, t0);
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break;
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case 4:
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if (((t0 ^ env->cr[4]) & CR4_LA57_MASK) &&
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(env->hflags & HF_CS64_MASK)) {
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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}
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cpu_x86_update_cr4(env, t0);
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break;
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case 8:
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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qemu_mutex_lock_iothread();
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cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0);
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qemu_mutex_unlock_iothread();
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}
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env->v_tpr = t0 & 0x0f;
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break;
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default:
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env->cr[reg] = t0;
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break;
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}
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}
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void helper_wrmsr(CPUX86State *env)
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{
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uint64_t val;
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CPUState *cs = env_cpu(env);
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
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val = ((uint32_t)env->regs[R_EAX]) |
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((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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switch ((uint32_t)env->regs[R_ECX]) {
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case MSR_IA32_SYSENTER_CS:
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env->sysenter_cs = val & 0xffff;
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break;
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case MSR_IA32_SYSENTER_ESP:
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env->sysenter_esp = val;
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break;
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case MSR_IA32_SYSENTER_EIP:
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env->sysenter_eip = val;
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break;
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case MSR_IA32_APICBASE:
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cpu_set_apic_base(env_archcpu(env)->apic_state, val);
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break;
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case MSR_EFER:
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{
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uint64_t update_mask;
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update_mask = 0;
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
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update_mask |= MSR_EFER_SCE;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
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update_mask |= MSR_EFER_LME;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
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update_mask |= MSR_EFER_FFXSR;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
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update_mask |= MSR_EFER_NXE;
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}
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if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
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update_mask |= MSR_EFER_SVME;
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
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update_mask |= MSR_EFER_FFXSR;
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}
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cpu_load_efer(env, (env->efer & ~update_mask) |
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(val & update_mask));
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}
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break;
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case MSR_STAR:
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env->star = val;
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break;
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case MSR_PAT:
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env->pat = val;
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break;
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case MSR_IA32_PKRS:
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if (val & 0xFFFFFFFF00000000ull) {
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goto error;
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}
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env->pkrs = val;
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tlb_flush(cs);
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break;
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case MSR_VM_HSAVE_PA:
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env->vm_hsave = val;
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break;
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#ifdef TARGET_X86_64
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case MSR_LSTAR:
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env->lstar = val;
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break;
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case MSR_CSTAR:
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env->cstar = val;
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break;
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case MSR_FMASK:
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env->fmask = val;
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break;
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case MSR_FSBASE:
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env->segs[R_FS].base = val;
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break;
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case MSR_GSBASE:
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env->segs[R_GS].base = val;
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break;
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case MSR_KERNELGSBASE:
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env->kernelgsbase = val;
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break;
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#endif
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case MSR_MTRRphysBase(0):
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case MSR_MTRRphysBase(1):
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case MSR_MTRRphysBase(2):
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case MSR_MTRRphysBase(3):
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case MSR_MTRRphysBase(4):
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case MSR_MTRRphysBase(5):
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case MSR_MTRRphysBase(6):
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case MSR_MTRRphysBase(7):
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env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysBase(0)) / 2].base = val;
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break;
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case MSR_MTRRphysMask(0):
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case MSR_MTRRphysMask(1):
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case MSR_MTRRphysMask(2):
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case MSR_MTRRphysMask(3):
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case MSR_MTRRphysMask(4):
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case MSR_MTRRphysMask(5):
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case MSR_MTRRphysMask(6):
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case MSR_MTRRphysMask(7):
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env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysMask(0)) / 2].mask = val;
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break;
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case MSR_MTRRfix64K_00000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix64K_00000] = val;
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break;
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case MSR_MTRRfix16K_80000:
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case MSR_MTRRfix16K_A0000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix16K_80000 + 1] = val;
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break;
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case MSR_MTRRfix4K_C0000:
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case MSR_MTRRfix4K_C8000:
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case MSR_MTRRfix4K_D0000:
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case MSR_MTRRfix4K_D8000:
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case MSR_MTRRfix4K_E0000:
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case MSR_MTRRfix4K_E8000:
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case MSR_MTRRfix4K_F0000:
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case MSR_MTRRfix4K_F8000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix4K_C0000 + 3] = val;
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break;
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case MSR_MTRRdefType:
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env->mtrr_deftype = val;
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break;
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case MSR_MCG_STATUS:
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env->mcg_status = val;
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break;
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case MSR_MCG_CTL:
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if ((env->mcg_cap & MCG_CTL_P)
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&& (val == 0 || val == ~(uint64_t)0)) {
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env->mcg_ctl = val;
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}
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break;
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case MSR_TSC_AUX:
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env->tsc_aux = val;
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break;
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case MSR_IA32_MISC_ENABLE:
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env->msr_ia32_misc_enable = val;
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break;
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case MSR_IA32_BNDCFGS:
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/* FIXME: #GP if reserved bits are set. */
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/* FIXME: Extend highest implemented bit of linear address. */
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env->msr_bndcfgs = val;
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cpu_sync_bndcs_hflags(env);
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break;
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default:
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if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
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(4 * env->mcg_cap & 0xff)) {
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uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
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if ((offset & 0x3) != 0
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|| (val == 0 || val == ~(uint64_t)0)) {
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env->mce_banks[offset] = val;
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}
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break;
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}
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/* XXX: exception? */
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break;
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}
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return;
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error:
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raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
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}
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void helper_rdmsr(CPUX86State *env)
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{
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X86CPU *x86_cpu = env_archcpu(env);
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uint64_t val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC());
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switch ((uint32_t)env->regs[R_ECX]) {
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case MSR_IA32_SYSENTER_CS:
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val = env->sysenter_cs;
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break;
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case MSR_IA32_SYSENTER_ESP:
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val = env->sysenter_esp;
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break;
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case MSR_IA32_SYSENTER_EIP:
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val = env->sysenter_eip;
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break;
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case MSR_IA32_APICBASE:
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val = cpu_get_apic_base(env_archcpu(env)->apic_state);
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break;
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case MSR_EFER:
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val = env->efer;
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break;
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case MSR_STAR:
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val = env->star;
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break;
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case MSR_PAT:
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val = env->pat;
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break;
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case MSR_IA32_PKRS:
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val = env->pkrs;
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break;
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case MSR_VM_HSAVE_PA:
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val = env->vm_hsave;
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break;
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case MSR_IA32_PERF_STATUS:
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/* tsc_increment_by_tick */
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val = 1000ULL;
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/* CPU multiplier */
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val |= (((uint64_t)4ULL) << 40);
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break;
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#ifdef TARGET_X86_64
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case MSR_LSTAR:
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val = env->lstar;
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break;
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case MSR_CSTAR:
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val = env->cstar;
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break;
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case MSR_FMASK:
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val = env->fmask;
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break;
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case MSR_FSBASE:
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val = env->segs[R_FS].base;
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break;
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case MSR_GSBASE:
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val = env->segs[R_GS].base;
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break;
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case MSR_KERNELGSBASE:
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val = env->kernelgsbase;
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break;
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case MSR_TSC_AUX:
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val = env->tsc_aux;
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break;
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#endif
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case MSR_SMI_COUNT:
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val = env->msr_smi_count;
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break;
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case MSR_MTRRphysBase(0):
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case MSR_MTRRphysBase(1):
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case MSR_MTRRphysBase(2):
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case MSR_MTRRphysBase(3):
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case MSR_MTRRphysBase(4):
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case MSR_MTRRphysBase(5):
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case MSR_MTRRphysBase(6):
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case MSR_MTRRphysBase(7):
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysBase(0)) / 2].base;
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break;
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case MSR_MTRRphysMask(0):
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case MSR_MTRRphysMask(1):
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case MSR_MTRRphysMask(2):
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case MSR_MTRRphysMask(3):
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case MSR_MTRRphysMask(4):
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case MSR_MTRRphysMask(5):
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case MSR_MTRRphysMask(6):
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case MSR_MTRRphysMask(7):
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysMask(0)) / 2].mask;
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break;
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case MSR_MTRRfix64K_00000:
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val = env->mtrr_fixed[0];
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break;
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case MSR_MTRRfix16K_80000:
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case MSR_MTRRfix16K_A0000:
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val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix16K_80000 + 1];
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break;
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case MSR_MTRRfix4K_C0000:
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case MSR_MTRRfix4K_C8000:
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case MSR_MTRRfix4K_D0000:
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case MSR_MTRRfix4K_D8000:
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case MSR_MTRRfix4K_E0000:
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case MSR_MTRRfix4K_E8000:
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case MSR_MTRRfix4K_F0000:
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case MSR_MTRRfix4K_F8000:
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val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix4K_C0000 + 3];
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break;
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case MSR_MTRRdefType:
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val = env->mtrr_deftype;
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break;
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case MSR_MTRRcap:
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if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
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val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
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MSR_MTRRcap_WC_SUPPORTED;
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} else {
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/* XXX: exception? */
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val = 0;
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}
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break;
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case MSR_MCG_CAP:
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val = env->mcg_cap;
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break;
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case MSR_MCG_CTL:
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if (env->mcg_cap & MCG_CTL_P) {
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val = env->mcg_ctl;
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} else {
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val = 0;
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}
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break;
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case MSR_MCG_STATUS:
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val = env->mcg_status;
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break;
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case MSR_IA32_MISC_ENABLE:
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val = env->msr_ia32_misc_enable;
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break;
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case MSR_IA32_BNDCFGS:
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val = env->msr_bndcfgs;
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break;
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case MSR_IA32_UCODE_REV:
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val = x86_cpu->ucode_rev;
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break;
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default:
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if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
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(4 * env->mcg_cap & 0xff)) {
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uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
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val = env->mce_banks[offset];
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break;
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}
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/* XXX: exception? */
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val = 0;
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break;
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}
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env->regs[R_EAX] = (uint32_t)(val);
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env->regs[R_EDX] = (uint32_t)(val >> 32);
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}
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void helper_invlpg(CPUX86State *env, target_ulong addr)
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{
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X86CPU *cpu = env_archcpu(env);
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cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
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tlb_flush_page(CPU(cpu), addr);
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}
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static void QEMU_NORETURN do_hlt(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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cpu_loop_exit(cs);
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}
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void QEMU_NORETURN helper_hlt(CPUX86State *env, int next_eip_addend)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
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env->eip += next_eip_addend;
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do_hlt(env);
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}
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void helper_monitor(CPUX86State *env, target_ulong ptr)
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{
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if ((uint32_t)env->regs[R_ECX] != 0) {
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
|
|
}
|
|
/* XXX: store address? */
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC());
|
|
}
|
|
|
|
void QEMU_NORETURN helper_mwait(CPUX86State *env, int next_eip_addend)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
if ((uint32_t)env->regs[R_ECX] != 0) {
|
|
raise_exception_ra(env, EXCP0D_GPF, GETPC());
|
|
}
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
|
|
env->eip += next_eip_addend;
|
|
|
|
/* XXX: not complete but not completely erroneous */
|
|
if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
|
|
do_pause(env);
|
|
} else {
|
|
do_hlt(env);
|
|
}
|
|
}
|