789 lines
22 KiB
C
789 lines
22 KiB
C
/*
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* ARM translation: M-profile MVE instructions
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*
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* Copyright (c) 2021 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "tcg/tcg-op-gvec.h"
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#include "exec/exec-all.h"
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#include "exec/gen-icount.h"
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#include "translate.h"
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#include "translate-a32.h"
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/* Include the generated decoder */
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#include "decode-mve.c.inc"
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typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
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typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
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typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
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typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
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/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
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static inline long mve_qreg_offset(unsigned reg)
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{
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return offsetof(CPUARMState, vfp.zregs[reg].d[0]);
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}
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static TCGv_ptr mve_qreg_ptr(unsigned reg)
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{
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TCGv_ptr ret = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg));
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return ret;
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}
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static bool mve_check_qreg_bank(DisasContext *s, int qmask)
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{
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/*
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* Check whether Qregs are in range. For v8.1M only Q0..Q7
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* are supported, see VFPSmallRegisterBank().
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*/
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return qmask < 8;
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}
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bool mve_eci_check(DisasContext *s)
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{
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/*
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* This is a beatwise insn: check that ECI is valid (not a
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* reserved value) and note that we are handling it.
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* Return true if OK, false if we generated an exception.
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*/
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s->eci_handled = true;
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switch (s->eci) {
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case ECI_NONE:
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case ECI_A0:
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case ECI_A0A1:
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case ECI_A0A1A2:
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case ECI_A0A1A2B0:
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return true;
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default:
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/* Reserved value: INVSTATE UsageFault */
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gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
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default_exception_el(s));
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return false;
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}
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}
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static void mve_update_eci(DisasContext *s)
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{
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/*
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* The helper function will always update the CPUState field,
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* so we only need to update the DisasContext field.
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*/
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if (s->eci) {
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s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE;
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}
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}
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void mve_update_and_store_eci(DisasContext *s)
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{
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/*
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* For insns which don't call a helper function that will call
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* mve_advance_vpt(), this version updates s->eci and also stores
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* it out to the CPUState field.
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*/
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if (s->eci) {
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mve_update_eci(s);
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store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits);
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}
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}
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static bool mve_skip_first_beat(DisasContext *s)
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{
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/* Return true if PSR.ECI says we must skip the first beat of this insn */
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switch (s->eci) {
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case ECI_NONE:
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return false;
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case ECI_A0:
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case ECI_A0A1:
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case ECI_A0A1A2:
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case ECI_A0A1A2B0:
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return true;
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default:
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g_assert_not_reached();
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}
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}
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static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
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{
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TCGv_i32 addr;
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uint32_t offset;
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TCGv_ptr qreg;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd) ||
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!fn) {
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return false;
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}
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/* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
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if (a->rn == 15 || (a->rn == 13 && a->w)) {
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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offset = a->imm << a->size;
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if (!a->a) {
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offset = -offset;
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}
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addr = load_reg(s, a->rn);
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if (a->p) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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qreg = mve_qreg_ptr(a->qd);
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fn(cpu_env, qreg, addr);
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tcg_temp_free_ptr(qreg);
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/*
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* Writeback always happens after the last beat of the insn,
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* regardless of predication
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*/
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if (a->w) {
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if (!a->p) {
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tcg_gen_addi_i32(addr, addr, offset);
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}
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store_reg(s, a->rn, addr);
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} else {
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tcg_temp_free_i32(addr);
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}
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mve_update_eci(s);
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return true;
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}
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static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
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{
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static MVEGenLdStFn * const ldstfns[4][2] = {
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{ gen_helper_mve_vstrb, gen_helper_mve_vldrb },
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{ gen_helper_mve_vstrh, gen_helper_mve_vldrh },
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{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
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{ NULL, NULL }
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};
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return do_ldst(s, a, ldstfns[a->size][a->l]);
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}
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#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
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static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
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{ \
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static MVEGenLdStFn * const ldstfns[2][2] = { \
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{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
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{ NULL, gen_helper_mve_##ULD }, \
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}; \
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return do_ldst(s, a, ldstfns[a->u][a->l]); \
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}
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DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
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DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
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DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
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static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
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{
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TCGv_ptr qd;
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TCGv_i32 rt;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd)) {
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return false;
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}
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if (a->rt == 13 || a->rt == 15) {
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/* UNPREDICTABLE; we choose to UNDEF */
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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qd = mve_qreg_ptr(a->qd);
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rt = load_reg(s, a->rt);
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tcg_gen_dup_i32(a->size, rt, rt);
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gen_helper_mve_vdup(cpu_env, qd, rt);
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tcg_temp_free_ptr(qd);
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tcg_temp_free_i32(rt);
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mve_update_eci(s);
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return true;
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}
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static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn)
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{
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TCGv_ptr qd, qm;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd | a->qm) ||
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!fn) {
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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qd = mve_qreg_ptr(a->qd);
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qm = mve_qreg_ptr(a->qm);
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fn(cpu_env, qd, qm);
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tcg_temp_free_ptr(qd);
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tcg_temp_free_ptr(qm);
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mve_update_eci(s);
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return true;
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}
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#define DO_1OP(INSN, FN) \
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static bool trans_##INSN(DisasContext *s, arg_1op *a) \
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{ \
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static MVEGenOneOpFn * const fns[] = { \
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gen_helper_mve_##FN##b, \
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gen_helper_mve_##FN##h, \
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gen_helper_mve_##FN##w, \
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NULL, \
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}; \
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return do_1op(s, a, fns[a->size]); \
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}
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DO_1OP(VCLZ, vclz)
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DO_1OP(VCLS, vcls)
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DO_1OP(VABS, vabs)
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DO_1OP(VNEG, vneg)
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static bool trans_VREV16(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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gen_helper_mve_vrev16b,
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NULL,
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NULL,
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NULL,
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};
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VREV32(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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gen_helper_mve_vrev32b,
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gen_helper_mve_vrev32h,
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NULL,
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NULL,
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};
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VREV64(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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gen_helper_mve_vrev64b,
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gen_helper_mve_vrev64h,
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gen_helper_mve_vrev64w,
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NULL,
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};
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VMVN(DisasContext *s, arg_1op *a)
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{
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return do_1op(s, a, gen_helper_mve_vmvn);
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}
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static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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NULL,
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gen_helper_mve_vfabsh,
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gen_helper_mve_vfabss,
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NULL,
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};
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if (!dc_isar_feature(aa32_mve_fp, s)) {
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return false;
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}
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return do_1op(s, a, fns[a->size]);
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}
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static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
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{
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static MVEGenOneOpFn * const fns[] = {
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NULL,
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gen_helper_mve_vfnegh,
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gen_helper_mve_vfnegs,
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NULL,
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};
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if (!dc_isar_feature(aa32_mve_fp, s)) {
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return false;
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}
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return do_1op(s, a, fns[a->size]);
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}
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static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
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{
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TCGv_ptr qd, qn, qm;
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if (!dc_isar_feature(aa32_mve, s) ||
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!mve_check_qreg_bank(s, a->qd | a->qn | a->qm) ||
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!fn) {
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return false;
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}
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if (!mve_eci_check(s) || !vfp_access_check(s)) {
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return true;
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}
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qd = mve_qreg_ptr(a->qd);
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qn = mve_qreg_ptr(a->qn);
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qm = mve_qreg_ptr(a->qm);
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fn(cpu_env, qd, qn, qm);
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tcg_temp_free_ptr(qd);
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tcg_temp_free_ptr(qn);
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tcg_temp_free_ptr(qm);
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mve_update_eci(s);
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return true;
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}
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#define DO_LOGIC(INSN, HELPER) \
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static bool trans_##INSN(DisasContext *s, arg_2op *a) \
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{ \
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return do_2op(s, a, HELPER); \
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}
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DO_LOGIC(VAND, gen_helper_mve_vand)
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DO_LOGIC(VBIC, gen_helper_mve_vbic)
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DO_LOGIC(VORR, gen_helper_mve_vorr)
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DO_LOGIC(VORN, gen_helper_mve_vorn)
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DO_LOGIC(VEOR, gen_helper_mve_veor)
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#define DO_2OP(INSN, FN) \
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static bool trans_##INSN(DisasContext *s, arg_2op *a) \
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{ \
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static MVEGenTwoOpFn * const fns[] = { \
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gen_helper_mve_##FN##b, \
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gen_helper_mve_##FN##h, \
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gen_helper_mve_##FN##w, \
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NULL, \
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}; \
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return do_2op(s, a, fns[a->size]); \
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}
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DO_2OP(VADD, vadd)
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DO_2OP(VSUB, vsub)
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DO_2OP(VMUL, vmul)
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DO_2OP(VMULH_S, vmulhs)
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DO_2OP(VMULH_U, vmulhu)
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DO_2OP(VRMULH_S, vrmulhs)
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DO_2OP(VRMULH_U, vrmulhu)
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DO_2OP(VMAX_S, vmaxs)
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DO_2OP(VMAX_U, vmaxu)
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DO_2OP(VMIN_S, vmins)
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DO_2OP(VMIN_U, vminu)
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DO_2OP(VABD_S, vabds)
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DO_2OP(VABD_U, vabdu)
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DO_2OP(VHADD_S, vhadds)
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DO_2OP(VHADD_U, vhaddu)
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DO_2OP(VHSUB_S, vhsubs)
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DO_2OP(VHSUB_U, vhsubu)
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DO_2OP(VMULL_BS, vmullbs)
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DO_2OP(VMULL_BU, vmullbu)
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DO_2OP(VMULL_TS, vmullts)
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DO_2OP(VMULL_TU, vmulltu)
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DO_2OP(VQDMULH, vqdmulh)
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DO_2OP(VQRDMULH, vqrdmulh)
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DO_2OP(VQADD_S, vqadds)
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DO_2OP(VQADD_U, vqaddu)
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DO_2OP(VQSUB_S, vqsubs)
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DO_2OP(VQSUB_U, vqsubu)
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DO_2OP(VSHL_S, vshls)
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DO_2OP(VSHL_U, vshlu)
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DO_2OP(VRSHL_S, vrshls)
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DO_2OP(VRSHL_U, vrshlu)
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DO_2OP(VQSHL_S, vqshls)
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DO_2OP(VQSHL_U, vqshlu)
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DO_2OP(VQRSHL_S, vqrshls)
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DO_2OP(VQRSHL_U, vqrshlu)
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DO_2OP(VQDMLADH, vqdmladh)
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DO_2OP(VQDMLADHX, vqdmladhx)
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DO_2OP(VQRDMLADH, vqrdmladh)
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DO_2OP(VQRDMLADHX, vqrdmladhx)
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DO_2OP(VQDMLSDH, vqdmlsdh)
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DO_2OP(VQDMLSDHX, vqdmlsdhx)
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DO_2OP(VQRDMLSDH, vqrdmlsdh)
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DO_2OP(VQRDMLSDHX, vqrdmlsdhx)
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DO_2OP(VRHADD_S, vrhadds)
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DO_2OP(VRHADD_U, vrhaddu)
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/*
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* VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose
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* so we can reuse the DO_2OP macro. (Our implementation calculates the
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* "expected" results in this case.) Similarly for VHCADD.
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*/
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DO_2OP(VCADD90, vcadd90)
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DO_2OP(VCADD270, vcadd270)
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DO_2OP(VHCADD90, vhcadd90)
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DO_2OP(VHCADD270, vhcadd270)
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static bool trans_VQDMULLB(DisasContext *s, arg_2op *a)
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{
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static MVEGenTwoOpFn * const fns[] = {
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NULL,
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gen_helper_mve_vqdmullbh,
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gen_helper_mve_vqdmullbw,
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NULL,
|
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};
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if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) {
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/* UNPREDICTABLE; we choose to undef */
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return false;
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}
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return do_2op(s, a, fns[a->size]);
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}
|
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|
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static bool trans_VQDMULLT(DisasContext *s, arg_2op *a)
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{
|
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static MVEGenTwoOpFn * const fns[] = {
|
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NULL,
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gen_helper_mve_vqdmullth,
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gen_helper_mve_vqdmulltw,
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NULL,
|
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};
|
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if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) {
|
|
/* UNPREDICTABLE; we choose to undef */
|
|
return false;
|
|
}
|
|
return do_2op(s, a, fns[a->size]);
|
|
}
|
|
|
|
/*
|
|
* VADC and VSBC: these perform an add-with-carry or subtract-with-carry
|
|
* of the 32-bit elements in each lane of the input vectors, where the
|
|
* carry-out of each add is the carry-in of the next. The initial carry
|
|
* input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C
|
|
* (for VADC and VSBC); the carry out at the end is written back to FPSCR.C.
|
|
* These insns are subject to beat-wise execution. Partial execution
|
|
* of an I=1 (initial carry input fixed) insn which does not
|
|
* execute the first beat must start with the current FPSCR.NZCV
|
|
* value, not the fixed constant input.
|
|
*/
|
|
static bool trans_VADC(DisasContext *s, arg_2op *a)
|
|
{
|
|
return do_2op(s, a, gen_helper_mve_vadc);
|
|
}
|
|
|
|
static bool trans_VADCI(DisasContext *s, arg_2op *a)
|
|
{
|
|
if (mve_skip_first_beat(s)) {
|
|
return trans_VADC(s, a);
|
|
}
|
|
return do_2op(s, a, gen_helper_mve_vadci);
|
|
}
|
|
|
|
static bool trans_VSBC(DisasContext *s, arg_2op *a)
|
|
{
|
|
return do_2op(s, a, gen_helper_mve_vsbc);
|
|
}
|
|
|
|
static bool trans_VSBCI(DisasContext *s, arg_2op *a)
|
|
{
|
|
if (mve_skip_first_beat(s)) {
|
|
return trans_VSBC(s, a);
|
|
}
|
|
return do_2op(s, a, gen_helper_mve_vsbci);
|
|
}
|
|
|
|
static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
|
|
MVEGenTwoOpScalarFn fn)
|
|
{
|
|
TCGv_ptr qd, qn;
|
|
TCGv_i32 rm;
|
|
|
|
if (!dc_isar_feature(aa32_mve, s) ||
|
|
!mve_check_qreg_bank(s, a->qd | a->qn) ||
|
|
!fn) {
|
|
return false;
|
|
}
|
|
if (a->rm == 13 || a->rm == 15) {
|
|
/* UNPREDICTABLE */
|
|
return false;
|
|
}
|
|
if (!mve_eci_check(s) || !vfp_access_check(s)) {
|
|
return true;
|
|
}
|
|
|
|
qd = mve_qreg_ptr(a->qd);
|
|
qn = mve_qreg_ptr(a->qn);
|
|
rm = load_reg(s, a->rm);
|
|
fn(cpu_env, qd, qn, rm);
|
|
tcg_temp_free_i32(rm);
|
|
tcg_temp_free_ptr(qd);
|
|
tcg_temp_free_ptr(qn);
|
|
mve_update_eci(s);
|
|
return true;
|
|
}
|
|
|
|
#define DO_2OP_SCALAR(INSN, FN) \
|
|
static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \
|
|
{ \
|
|
static MVEGenTwoOpScalarFn * const fns[] = { \
|
|
gen_helper_mve_##FN##b, \
|
|
gen_helper_mve_##FN##h, \
|
|
gen_helper_mve_##FN##w, \
|
|
NULL, \
|
|
}; \
|
|
return do_2op_scalar(s, a, fns[a->size]); \
|
|
}
|
|
|
|
DO_2OP_SCALAR(VADD_scalar, vadd_scalar)
|
|
DO_2OP_SCALAR(VSUB_scalar, vsub_scalar)
|
|
DO_2OP_SCALAR(VMUL_scalar, vmul_scalar)
|
|
DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar)
|
|
DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar)
|
|
DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar)
|
|
DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar)
|
|
DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar)
|
|
DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar)
|
|
DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar)
|
|
DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar)
|
|
DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar)
|
|
DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar)
|
|
DO_2OP_SCALAR(VBRSR, vbrsr)
|
|
|
|
static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a)
|
|
{
|
|
static MVEGenTwoOpScalarFn * const fns[] = {
|
|
NULL,
|
|
gen_helper_mve_vqdmullb_scalarh,
|
|
gen_helper_mve_vqdmullb_scalarw,
|
|
NULL,
|
|
};
|
|
if (a->qd == a->qn && a->size == MO_32) {
|
|
/* UNPREDICTABLE; we choose to undef */
|
|
return false;
|
|
}
|
|
return do_2op_scalar(s, a, fns[a->size]);
|
|
}
|
|
|
|
static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a)
|
|
{
|
|
static MVEGenTwoOpScalarFn * const fns[] = {
|
|
NULL,
|
|
gen_helper_mve_vqdmullt_scalarh,
|
|
gen_helper_mve_vqdmullt_scalarw,
|
|
NULL,
|
|
};
|
|
if (a->qd == a->qn && a->size == MO_32) {
|
|
/* UNPREDICTABLE; we choose to undef */
|
|
return false;
|
|
}
|
|
return do_2op_scalar(s, a, fns[a->size]);
|
|
}
|
|
|
|
static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
|
|
MVEGenDualAccOpFn *fn)
|
|
{
|
|
TCGv_ptr qn, qm;
|
|
TCGv_i64 rda;
|
|
TCGv_i32 rdalo, rdahi;
|
|
|
|
if (!dc_isar_feature(aa32_mve, s) ||
|
|
!mve_check_qreg_bank(s, a->qn | a->qm) ||
|
|
!fn) {
|
|
return false;
|
|
}
|
|
/*
|
|
* rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
|
|
* encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
|
|
*/
|
|
if (a->rdahi == 13 || a->rdahi == 15) {
|
|
return false;
|
|
}
|
|
if (!mve_eci_check(s) || !vfp_access_check(s)) {
|
|
return true;
|
|
}
|
|
|
|
qn = mve_qreg_ptr(a->qn);
|
|
qm = mve_qreg_ptr(a->qm);
|
|
|
|
/*
|
|
* This insn is subject to beat-wise execution. Partial execution
|
|
* of an A=0 (no-accumulate) insn which does not execute the first
|
|
* beat must start with the current rda value, not 0.
|
|
*/
|
|
if (a->a || mve_skip_first_beat(s)) {
|
|
rda = tcg_temp_new_i64();
|
|
rdalo = load_reg(s, a->rdalo);
|
|
rdahi = load_reg(s, a->rdahi);
|
|
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
|
|
tcg_temp_free_i32(rdalo);
|
|
tcg_temp_free_i32(rdahi);
|
|
} else {
|
|
rda = tcg_const_i64(0);
|
|
}
|
|
|
|
fn(rda, cpu_env, qn, qm, rda);
|
|
tcg_temp_free_ptr(qn);
|
|
tcg_temp_free_ptr(qm);
|
|
|
|
rdalo = tcg_temp_new_i32();
|
|
rdahi = tcg_temp_new_i32();
|
|
tcg_gen_extrl_i64_i32(rdalo, rda);
|
|
tcg_gen_extrh_i64_i32(rdahi, rda);
|
|
store_reg(s, a->rdalo, rdalo);
|
|
store_reg(s, a->rdahi, rdahi);
|
|
tcg_temp_free_i64(rda);
|
|
mve_update_eci(s);
|
|
return true;
|
|
}
|
|
|
|
static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a)
|
|
{
|
|
static MVEGenDualAccOpFn * const fns[4][2] = {
|
|
{ NULL, NULL },
|
|
{ gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh },
|
|
{ gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw },
|
|
{ NULL, NULL },
|
|
};
|
|
return do_long_dual_acc(s, a, fns[a->size][a->x]);
|
|
}
|
|
|
|
static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a)
|
|
{
|
|
static MVEGenDualAccOpFn * const fns[4][2] = {
|
|
{ NULL, NULL },
|
|
{ gen_helper_mve_vmlaldavuh, NULL },
|
|
{ gen_helper_mve_vmlaldavuw, NULL },
|
|
{ NULL, NULL },
|
|
};
|
|
return do_long_dual_acc(s, a, fns[a->size][a->x]);
|
|
}
|
|
|
|
static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a)
|
|
{
|
|
static MVEGenDualAccOpFn * const fns[4][2] = {
|
|
{ NULL, NULL },
|
|
{ gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh },
|
|
{ gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw },
|
|
{ NULL, NULL },
|
|
};
|
|
return do_long_dual_acc(s, a, fns[a->size][a->x]);
|
|
}
|
|
|
|
static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a)
|
|
{
|
|
static MVEGenDualAccOpFn * const fns[] = {
|
|
gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw,
|
|
};
|
|
return do_long_dual_acc(s, a, fns[a->x]);
|
|
}
|
|
|
|
static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a)
|
|
{
|
|
static MVEGenDualAccOpFn * const fns[] = {
|
|
gen_helper_mve_vrmlaldavhuw, NULL,
|
|
};
|
|
return do_long_dual_acc(s, a, fns[a->x]);
|
|
}
|
|
|
|
static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
|
|
{
|
|
static MVEGenDualAccOpFn * const fns[] = {
|
|
gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw,
|
|
};
|
|
return do_long_dual_acc(s, a, fns[a->x]);
|
|
}
|
|
|
|
static bool trans_VPST(DisasContext *s, arg_VPST *a)
|
|
{
|
|
TCGv_i32 vpr;
|
|
|
|
/* mask == 0 is a "related encoding" */
|
|
if (!dc_isar_feature(aa32_mve, s) || !a->mask) {
|
|
return false;
|
|
}
|
|
if (!mve_eci_check(s) || !vfp_access_check(s)) {
|
|
return true;
|
|
}
|
|
/*
|
|
* Set the VPR mask fields. We take advantage of MASK01 and MASK23
|
|
* being adjacent fields in the register.
|
|
*
|
|
* This insn is not predicated, but it is subject to beat-wise
|
|
* execution, and the mask is updated on the odd-numbered beats.
|
|
* So if PSR.ECI says we should skip beat 1, we mustn't update the
|
|
* 01 mask field.
|
|
*/
|
|
vpr = load_cpu_field(v7m.vpr);
|
|
switch (s->eci) {
|
|
case ECI_NONE:
|
|
case ECI_A0:
|
|
/* Update both 01 and 23 fields */
|
|
tcg_gen_deposit_i32(vpr, vpr,
|
|
tcg_constant_i32(a->mask | (a->mask << 4)),
|
|
R_V7M_VPR_MASK01_SHIFT,
|
|
R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH);
|
|
break;
|
|
case ECI_A0A1:
|
|
case ECI_A0A1A2:
|
|
case ECI_A0A1A2B0:
|
|
/* Update only the 23 mask field */
|
|
tcg_gen_deposit_i32(vpr, vpr,
|
|
tcg_constant_i32(a->mask),
|
|
R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
store_cpu_field(vpr, v7m.vpr);
|
|
mve_update_and_store_eci(s);
|
|
return true;
|
|
}
|
|
|
|
static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
|
|
{
|
|
/* VADDV: vector add across vector */
|
|
static MVEGenVADDVFn * const fns[4][2] = {
|
|
{ gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub },
|
|
{ gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh },
|
|
{ gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw },
|
|
{ NULL, NULL }
|
|
};
|
|
TCGv_ptr qm;
|
|
TCGv_i32 rda;
|
|
|
|
if (!dc_isar_feature(aa32_mve, s) ||
|
|
a->size == 3) {
|
|
return false;
|
|
}
|
|
if (!mve_eci_check(s) || !vfp_access_check(s)) {
|
|
return true;
|
|
}
|
|
|
|
/*
|
|
* This insn is subject to beat-wise execution. Partial execution
|
|
* of an A=0 (no-accumulate) insn which does not execute the first
|
|
* beat must start with the current value of Rda, not zero.
|
|
*/
|
|
if (a->a || mve_skip_first_beat(s)) {
|
|
/* Accumulate input from Rda */
|
|
rda = load_reg(s, a->rda);
|
|
} else {
|
|
/* Accumulate starting at zero */
|
|
rda = tcg_const_i32(0);
|
|
}
|
|
|
|
qm = mve_qreg_ptr(a->qm);
|
|
fns[a->size][a->u](rda, cpu_env, qm, rda);
|
|
store_reg(s, a->rda, rda);
|
|
tcg_temp_free_ptr(qm);
|
|
|
|
mve_update_eci(s);
|
|
return true;
|
|
}
|