OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity
qemu-e2k/hw/riscv
History
Bin Meng 722f1352b6 hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card 
This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.

Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
Note subsequent payload is stored in the SD card image.

$ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \
    -bios u-boot-spl.bin -drive file=sdcard.img,if=sd

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2021-03-04 09:43:29 -05:00
..
Kconfig hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card 2021-03-04 09:43:29 -05:00
boot.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
meson.build hw/riscv: Always build riscv_hart.c 2020-09-09 15:54:19 -07:00
microchip_pfsoc.c hw/riscv: microchip_pfsoc: add QSPI NOR flash 2020-12-17 21:56:43 -08:00
numa.c hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.c riscv/opentitan: Update the OpenTitan memory layout 2020-12-17 21:56:44 -08:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
sifive_e.c hw/riscv: Load the kernel after the firmware 2020-10-22 12:00:22 -07:00
sifive_u.c hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card 2021-03-04 09:43:29 -05:00
spike.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
virt.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00