qemu-e2k/target/ppc
Fabiano Rosas 5609400a42 target/ppc: Set the correct endianness for powernv memory dumps
We use the endianness of interrupts to determine which endianness to
use for the guest kernel memory dump. For machines that support HILE
(powernv8 and up) we have been always generating big endian dump
files.

This patch uses the HILE support recently added to
ppc_interrupts_little_endian to fix the endianness of the dumps for
powernv machines.

Here are two dumps created at different moments:

$ file skiboot.dump
skiboot.dump: ELF 64-bit MSB core file, 64-bit PowerPC ...

$ file kernel.dump
kernel.dump: ELF 64-bit LSB core file, 64-bit PowerPC ...

Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12 11:28:27 +01:00
..
translate exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
Kconfig
arch_dump.c target/ppc: Set the correct endianness for powernv memory dumps 2022-01-12 11:28:27 +01:00
compat.c
cpu-models.c target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
cpu-models.h target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
cpu-param.h
cpu-qom.h target/ppc: remove 401/403 CPUs 2021-12-17 17:57:16 +01:00
cpu.c target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52 2021-12-17 17:57:13 +01:00
cpu.h target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian 2022-01-12 11:28:27 +01:00
cpu_init.c target/ppc: Add extra float instructions to POWER5P processors 2022-01-12 11:28:26 +01:00
dfp_helper.c target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree 2021-11-09 10:32:52 +11:00
excp_helper.c target/ppc: Introduce a wrapper for powerpc_excp 2022-01-12 11:28:27 +01:00
fpu_helper.c target/ppc: do not silence snan in xscvspdpn 2022-01-04 07:55:34 +01:00
gdbstub.c
helper.h ppc/ppc405: Restore TCR and STR write handlers 2022-01-04 07:55:34 +01:00
helper_regs.c target/ppc: Cache per-pmc insn and cycle count settings 2022-01-04 07:55:34 +01:00
helper_regs.h
insn32.decode PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
insn64.decode target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions 2021-11-09 10:32:53 +11:00
int_helper.c target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions 2021-11-09 10:32:53 +11:00
internal.h target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu 2021-11-02 07:00:52 -04:00
kvm-stub.c
kvm.c
kvm_ppc.h
machine.c target/ppc: Cache per-pmc insn and cycle count settings 2022-01-04 07:55:34 +01:00
mem_helper.c
meson.build target/ppc: introduce PMUEventType and PMU overflow timers 2021-12-17 17:57:18 +01:00
mfrom_table.c.inc
mfrom_table_gen.c
misc_helper.c
mmu-book3s-v3.c
mmu-book3s-v3.h
mmu-books.h
mmu-hash32.c
mmu-hash32.h
mmu-hash64.c target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
mmu-hash64.h target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
mmu-radix64.c target/ppc: Check effective address validity 2022-01-04 07:55:34 +01:00
mmu-radix64.h target/ppc: Check effective address validity 2022-01-04 07:55:34 +01:00
mmu_common.c ppc/ppc405: Activate MMU logs 2022-01-04 07:55:34 +01:00
mmu_helper.c ppc/ppc405: Activate MMU logs 2022-01-04 07:55:34 +01:00
monitor.c
power8-pmu-regs.c.inc target/ppc: enable PMU instruction count 2021-12-17 17:57:18 +01:00
power8-pmu.c target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0() 2022-01-04 07:55:35 +01:00
power8-pmu.h target/ppc: Cache per-pmc insn and cycle count settings 2022-01-04 07:55:34 +01:00
spr_tcg.h ppc/ppc405: Introduce a store helper for SPR_40x_PID 2022-01-04 07:55:34 +01:00
tcg-stub.c
timebase_helper.c ppc/ppc405: Restore TCR and STR write handlers 2022-01-04 07:55:34 +01:00
trace-events
trace.h
translate.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
user_only_helper.c target/ppc: Implement ppc_cpu_record_sigsegv 2021-11-02 07:00:52 -04:00