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qemu-e2k/hw/riscv
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Alistair Francis 9ae6ecd848 hw/riscv: shakti_c: Mark as not user creatable 
Mark the shakti_c machine as not user creatable.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
 		2021-10-07 08:41:33 +10:00
..
Kconfig hw/intc: Rename sifive_clint sources to riscv_aclint sources 2021-09-21 07:56:49 +10:00
boot.c hw/riscv/boot: Check the error of fdt_pack() 2021-07-15 09:35:46 +10:00
meson.build hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines 2021-07-20 15:32:49 +02:00
microchip_pfsoc.c hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT 2021-09-21 07:56:49 +10:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/riscv: opentitan: Correct the USB Dev address 2021-09-21 12:10:47 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: shakti_c: Mark as not user creatable 2021-10-07 08:41:33 +10:00
sifive_e.c hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT 2021-09-21 07:56:49 +10:00
sifive_u.c hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT 2021-09-21 07:56:49 +10:00
spike.c hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT 2021-09-21 07:56:49 +10:00
virt.c hw/riscv: virt: Add optional ACLINT support to virt machine 2021-09-21 07:56:49 +10:00