51806b5458
Create one common dispatch for all of the ppc_*_xlate functions. Use ppc64_v3_radix to directly dispatch between ppc_radix64_xlate and ppc_hash64_xlate. Remove the separate *_handle_mmu_fault and *_get_phys_page_debug functions, using common code for ppc_cpu_tlb_fill and ppc_cpu_get_phys_page_debug. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210621125115.67717-9-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
117 lines
3.1 KiB
C
117 lines
3.1 KiB
C
/*
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* PowerPC ISAV3 BookS emulation generic mmu definitions for qemu.
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*
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* Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_MMU_BOOK3S_V3_H
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#define PPC_MMU_BOOK3S_V3_H
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#include "mmu-hash64.h"
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#ifndef CONFIG_USER_ONLY
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/*
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* Partition table definitions
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*/
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#define PTCR_PATB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
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#define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
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/* Partition Table Entry Fields */
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#define PATE0_HR 0x8000000000000000
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/*
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* WARNING: This field doesn't actually exist in the final version of
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* the architecture and is unused by hardware. However, qemu uses it
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* as an indication of a radix guest in the pseudo-PATB entry that it
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* maintains for SPAPR guests and in the migration stream, so we need
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* to keep it around
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*/
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#define PATE1_GR 0x8000000000000000
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/* Process Table Entry */
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struct prtb_entry {
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uint64_t prtbe0, prtbe1;
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};
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#ifdef TARGET_PPC64
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static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
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{
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return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
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}
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bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
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ppc_v3_pate_t *entry);
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/*
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* The LPCR:HR bit is a shortcut that avoids having to
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* dig out the partition table in the fast path. This is
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* also how the HW uses it.
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*/
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static inline bool ppc64_v3_radix(PowerPCCPU *cpu)
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{
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return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR);
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}
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static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
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{
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uint64_t base;
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if (cpu->vhyp) {
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return 0;
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}
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if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
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ppc_v3_pate_t pate;
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if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
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return 0;
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}
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base = pate.dw0;
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} else {
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base = cpu->env.spr[SPR_SDR1];
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}
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return base & SDR_64_HTABORG;
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}
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static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
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{
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uint64_t base;
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if (cpu->vhyp) {
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PPCVirtualHypervisorClass *vhc =
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PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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return vhc->hpt_mask(cpu->vhyp);
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}
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if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
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ppc_v3_pate_t pate;
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if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
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return 0;
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}
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base = pate.dw0;
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} else {
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base = cpu->env.spr[SPR_SDR1];
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}
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return (1ULL << ((base & SDR_64_HTABSIZE) + 18 - 7)) - 1;
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}
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#endif /* TARGET_PPC64 */
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#endif /* CONFIG_USER_ONLY */
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#endif /* PPC_MMU_BOOK3S_V3_H */
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