5183f209eb
This reverts commit dc09f047ed.
For tcg, tracepoints are expanded inline in tcg opcodes.
Using a helper which generates a second tracepoint is incorrect.
For system mode, the extraction and re-packing of MemOp and mmu_idx
lost the alignment information from MemOp. So we were no longer
raising alignment exceptions for !TARGET_ALIGNED_ONLY guests.
This can be seen in tests/tcg/xtensa/test_load_store.S.
For user mode, we must update to the new signature of g2h() so that
the revert compiles. We can leave set_helper_retaddr for later.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
1363 lines
42 KiB
C
1363 lines
42 KiB
C
/*
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* Tiny Code Interpreter for QEMU
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*
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* Copyright (c) 2009, 2011, 2016 Stefan Weil
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
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#include "exec/cpu_ldst.h"
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#include "tcg/tcg-op.h"
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#include "qemu/compiler.h"
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#include <ffi.h>
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/*
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* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
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* Without assertions, the interpreter runs much faster.
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*/
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#if defined(CONFIG_DEBUG_TCG)
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# define tci_assert(cond) assert(cond)
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#else
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# define tci_assert(cond) ((void)(cond))
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#endif
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__thread uintptr_t tci_tb_ptr;
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static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
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uint32_t low_index, uint64_t value)
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{
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regs[low_index] = (uint32_t)value;
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regs[high_index] = value >> 32;
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}
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/* Create a 64 bit value from two 32 bit values. */
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static uint64_t tci_uint64(uint32_t high, uint32_t low)
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{
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return ((uint64_t)high << 32) + low;
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}
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/*
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* Load sets of arguments all at once. The naming convention is:
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* tci_args_<arguments>
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* where arguments is a sequence of
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*
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* b = immediate (bit position)
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* c = condition (TCGCond)
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* i = immediate (uint32_t)
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* I = immediate (tcg_target_ulong)
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* l = label or pointer
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* m = immediate (TCGMemOpIdx)
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* n = immediate (call return length)
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* r = register
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* s = signed ldst offset
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*/
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static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0)
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{
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int diff = sextract32(insn, 12, 20);
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*l0 = diff ? (void *)tb_ptr + diff : NULL;
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}
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static void tci_args_r(uint32_t insn, TCGReg *r0)
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{
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*r0 = extract32(insn, 8, 4);
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}
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static void tci_args_nl(uint32_t insn, const void *tb_ptr,
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uint8_t *n0, void **l1)
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{
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*n0 = extract32(insn, 8, 4);
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*l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
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}
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static void tci_args_rl(uint32_t insn, const void *tb_ptr,
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TCGReg *r0, void **l1)
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{
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*r0 = extract32(insn, 8, 4);
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*l1 = sextract32(insn, 12, 20) + (void *)tb_ptr;
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}
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static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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}
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static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
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{
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*r0 = extract32(insn, 8, 4);
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*i1 = sextract32(insn, 12, 20);
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}
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static void tci_args_rrm(uint32_t insn, TCGReg *r0,
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TCGReg *r1, TCGMemOpIdx *m2)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*m2 = extract32(insn, 20, 12);
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}
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static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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}
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static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*i2 = sextract32(insn, 16, 16);
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}
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static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
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uint8_t *i2, uint8_t *i3)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*i2 = extract32(insn, 16, 6);
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*i3 = extract32(insn, 22, 6);
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}
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static void tci_args_rrrc(uint32_t insn,
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TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*c3 = extract32(insn, 20, 4);
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}
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static void tci_args_rrrm(uint32_t insn,
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TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*m3 = extract32(insn, 20, 12);
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}
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static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1,
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TCGReg *r2, uint8_t *i3, uint8_t *i4)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*i3 = extract32(insn, 20, 6);
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*i4 = extract32(insn, 26, 6);
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}
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static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
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TCGReg *r2, TCGReg *r3, TCGReg *r4)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*r3 = extract32(insn, 20, 4);
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*r4 = extract32(insn, 24, 4);
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}
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static void tci_args_rrrr(uint32_t insn,
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TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*r3 = extract32(insn, 20, 4);
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}
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static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1,
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TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*r3 = extract32(insn, 20, 4);
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*r4 = extract32(insn, 24, 4);
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*c5 = extract32(insn, 28, 4);
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}
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static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1,
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TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
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{
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*r0 = extract32(insn, 8, 4);
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*r1 = extract32(insn, 12, 4);
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*r2 = extract32(insn, 16, 4);
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*r3 = extract32(insn, 20, 4);
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*r4 = extract32(insn, 24, 4);
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*r5 = extract32(insn, 28, 4);
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}
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static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
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{
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bool result = false;
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int32_t i0 = u0;
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int32_t i1 = u1;
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switch (condition) {
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case TCG_COND_EQ:
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result = (u0 == u1);
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break;
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case TCG_COND_NE:
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result = (u0 != u1);
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break;
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case TCG_COND_LT:
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result = (i0 < i1);
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break;
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case TCG_COND_GE:
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result = (i0 >= i1);
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break;
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case TCG_COND_LE:
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result = (i0 <= i1);
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break;
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case TCG_COND_GT:
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result = (i0 > i1);
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break;
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case TCG_COND_LTU:
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result = (u0 < u1);
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break;
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case TCG_COND_GEU:
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result = (u0 >= u1);
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break;
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case TCG_COND_LEU:
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result = (u0 <= u1);
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break;
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case TCG_COND_GTU:
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result = (u0 > u1);
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break;
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default:
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g_assert_not_reached();
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}
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return result;
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}
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static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
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{
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bool result = false;
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int64_t i0 = u0;
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int64_t i1 = u1;
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switch (condition) {
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case TCG_COND_EQ:
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result = (u0 == u1);
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break;
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case TCG_COND_NE:
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result = (u0 != u1);
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break;
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case TCG_COND_LT:
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result = (i0 < i1);
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break;
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case TCG_COND_GE:
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result = (i0 >= i1);
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break;
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case TCG_COND_LE:
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result = (i0 <= i1);
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break;
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case TCG_COND_GT:
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result = (i0 > i1);
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break;
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case TCG_COND_LTU:
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result = (u0 < u1);
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break;
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case TCG_COND_GEU:
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result = (u0 >= u1);
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break;
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case TCG_COND_LEU:
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result = (u0 <= u1);
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break;
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case TCG_COND_GTU:
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result = (u0 > u1);
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break;
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default:
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g_assert_not_reached();
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}
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return result;
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}
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#ifdef CONFIG_SOFTMMU
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# define qemu_ld_ub \
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helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_ld_leuw \
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helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_ld_leul \
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helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_ld_leq \
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helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_ld_beuw \
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helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_ld_beul \
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helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_ld_beq \
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helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
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# define qemu_st_b(X) \
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helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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# define qemu_st_lew(X) \
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helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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# define qemu_st_lel(X) \
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helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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# define qemu_st_leq(X) \
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helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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# define qemu_st_bew(X) \
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helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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# define qemu_st_bel(X) \
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helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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# define qemu_st_beq(X) \
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helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
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#else
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# define qemu_ld_ub ldub_p(g2h(env_cpu(env), taddr))
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# define qemu_ld_leuw lduw_le_p(g2h(env_cpu(env), taddr))
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# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(env_cpu(env), taddr))
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# define qemu_ld_leq ldq_le_p(g2h(env_cpu(env), taddr))
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# define qemu_ld_beuw lduw_be_p(g2h(env_cpu(env), taddr))
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# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(env_cpu(env), taddr))
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# define qemu_ld_beq ldq_be_p(g2h(env_cpu(env), taddr))
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# define qemu_st_b(X) stb_p(g2h(env_cpu(env), taddr), X)
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# define qemu_st_lew(X) stw_le_p(g2h(env_cpu(env), taddr), X)
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# define qemu_st_lel(X) stl_le_p(g2h(env_cpu(env), taddr), X)
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# define qemu_st_leq(X) stq_le_p(g2h(env_cpu(env), taddr), X)
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# define qemu_st_bew(X) stw_be_p(g2h(env_cpu(env), taddr), X)
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# define qemu_st_bel(X) stl_be_p(g2h(env_cpu(env), taddr), X)
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# define qemu_st_beq(X) stq_be_p(g2h(env_cpu(env), taddr), X)
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#endif
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static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
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TCGMemOpIdx oi, const void *tb_ptr)
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{
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MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
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switch (mop) {
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case MO_UB:
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return qemu_ld_ub;
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case MO_SB:
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return (int8_t)qemu_ld_ub;
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case MO_LEUW:
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return qemu_ld_leuw;
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case MO_LESW:
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return (int16_t)qemu_ld_leuw;
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case MO_LEUL:
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return qemu_ld_leul;
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case MO_LESL:
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return (int32_t)qemu_ld_leul;
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case MO_LEQ:
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return qemu_ld_leq;
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case MO_BEUW:
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return qemu_ld_beuw;
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case MO_BESW:
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return (int16_t)qemu_ld_beuw;
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case MO_BEUL:
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return qemu_ld_beul;
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case MO_BESL:
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return (int32_t)qemu_ld_beul;
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case MO_BEQ:
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return qemu_ld_beq;
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default:
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g_assert_not_reached();
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}
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}
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static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
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TCGMemOpIdx oi, const void *tb_ptr)
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{
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MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
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switch (mop) {
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case MO_UB:
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qemu_st_b(val);
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break;
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case MO_LEUW:
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qemu_st_lew(val);
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break;
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case MO_LEUL:
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qemu_st_lel(val);
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break;
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case MO_LEQ:
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qemu_st_leq(val);
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break;
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case MO_BEUW:
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qemu_st_bew(val);
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break;
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case MO_BEUL:
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qemu_st_bel(val);
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break;
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case MO_BEQ:
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qemu_st_beq(val);
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break;
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default:
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g_assert_not_reached();
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}
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}
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#if TCG_TARGET_REG_BITS == 64
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# define CASE_32_64(x) \
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case glue(glue(INDEX_op_, x), _i64): \
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case glue(glue(INDEX_op_, x), _i32):
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# define CASE_64(x) \
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case glue(glue(INDEX_op_, x), _i64):
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#else
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# define CASE_32_64(x) \
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case glue(glue(INDEX_op_, x), _i32):
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# define CASE_64(x)
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#endif
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/* Interpret pseudo code in tb. */
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/*
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* Disable CFI checks.
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* One possible operation in the pseudo code is a call to binary code.
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* Therefore, disable CFI checks in the interpreter function
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*/
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uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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const void *v_tb_ptr)
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{
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const uint32_t *tb_ptr = v_tb_ptr;
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tcg_target_ulong regs[TCG_TARGET_NB_REGS];
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uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE)
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/ sizeof(uint64_t)];
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void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)];
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regs[TCG_AREG0] = (tcg_target_ulong)env;
|
|
regs[TCG_REG_CALL_STACK] = (uintptr_t)stack;
|
|
/* Other call_slots entries initialized at first use (see below). */
|
|
call_slots[0] = NULL;
|
|
tci_assert(tb_ptr);
|
|
|
|
for (;;) {
|
|
uint32_t insn;
|
|
TCGOpcode opc;
|
|
TCGReg r0, r1, r2, r3, r4, r5;
|
|
tcg_target_ulong t1;
|
|
TCGCond condition;
|
|
target_ulong taddr;
|
|
uint8_t pos, len;
|
|
uint32_t tmp32;
|
|
uint64_t tmp64;
|
|
uint64_t T1, T2;
|
|
TCGMemOpIdx oi;
|
|
int32_t ofs;
|
|
void *ptr;
|
|
|
|
insn = *tb_ptr++;
|
|
opc = extract32(insn, 0, 8);
|
|
|
|
switch (opc) {
|
|
case INDEX_op_call:
|
|
/*
|
|
* Set up the ffi_avalue array once, delayed until now
|
|
* because many TB's do not make any calls. In tcg_gen_callN,
|
|
* we arranged for every real argument to be "left-aligned"
|
|
* in each 64-bit slot.
|
|
*/
|
|
if (unlikely(call_slots[0] == NULL)) {
|
|
for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) {
|
|
call_slots[i] = &stack[i];
|
|
}
|
|
}
|
|
|
|
tci_args_nl(insn, tb_ptr, &len, &ptr);
|
|
|
|
/* Helper functions may need to access the "return address" */
|
|
tci_tb_ptr = (uintptr_t)tb_ptr;
|
|
|
|
{
|
|
void **pptr = ptr;
|
|
ffi_call(pptr[1], pptr[0], stack, call_slots);
|
|
}
|
|
|
|
/* Any result winds up "left-aligned" in the stack[0] slot. */
|
|
switch (len) {
|
|
case 0: /* void */
|
|
break;
|
|
case 1: /* uint32_t */
|
|
/*
|
|
* Note that libffi has an odd special case in that it will
|
|
* always widen an integral result to ffi_arg.
|
|
*/
|
|
if (sizeof(ffi_arg) == 4) {
|
|
regs[TCG_REG_R0] = *(uint32_t *)stack;
|
|
break;
|
|
}
|
|
/* fall through */
|
|
case 2: /* uint64_t */
|
|
if (TCG_TARGET_REG_BITS == 32) {
|
|
tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]);
|
|
} else {
|
|
regs[TCG_REG_R0] = stack[0];
|
|
}
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
break;
|
|
|
|
case INDEX_op_br:
|
|
tci_args_l(insn, tb_ptr, &ptr);
|
|
tb_ptr = ptr;
|
|
continue;
|
|
case INDEX_op_setcond_i32:
|
|
tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
|
|
regs[r0] = tci_compare32(regs[r1], regs[r2], condition);
|
|
break;
|
|
case INDEX_op_movcond_i32:
|
|
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
|
|
tmp32 = tci_compare32(regs[r1], regs[r2], condition);
|
|
regs[r0] = regs[tmp32 ? r3 : r4];
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
case INDEX_op_setcond2_i32:
|
|
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
|
|
T1 = tci_uint64(regs[r2], regs[r1]);
|
|
T2 = tci_uint64(regs[r4], regs[r3]);
|
|
regs[r0] = tci_compare64(T1, T2, condition);
|
|
break;
|
|
#elif TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_setcond_i64:
|
|
tci_args_rrrc(insn, &r0, &r1, &r2, &condition);
|
|
regs[r0] = tci_compare64(regs[r1], regs[r2], condition);
|
|
break;
|
|
case INDEX_op_movcond_i64:
|
|
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
|
|
tmp32 = tci_compare64(regs[r1], regs[r2], condition);
|
|
regs[r0] = regs[tmp32 ? r3 : r4];
|
|
break;
|
|
#endif
|
|
CASE_32_64(mov)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = regs[r1];
|
|
break;
|
|
case INDEX_op_tci_movi:
|
|
tci_args_ri(insn, &r0, &t1);
|
|
regs[r0] = t1;
|
|
break;
|
|
case INDEX_op_tci_movl:
|
|
tci_args_rl(insn, tb_ptr, &r0, &ptr);
|
|
regs[r0] = *(tcg_target_ulong *)ptr;
|
|
break;
|
|
|
|
/* Load/store operations (32 bit). */
|
|
|
|
CASE_32_64(ld8u)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(uint8_t *)ptr;
|
|
break;
|
|
CASE_32_64(ld8s)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(int8_t *)ptr;
|
|
break;
|
|
CASE_32_64(ld16u)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(uint16_t *)ptr;
|
|
break;
|
|
CASE_32_64(ld16s)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(int16_t *)ptr;
|
|
break;
|
|
case INDEX_op_ld_i32:
|
|
CASE_64(ld32u)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(uint32_t *)ptr;
|
|
break;
|
|
CASE_32_64(st8)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
*(uint8_t *)ptr = regs[r0];
|
|
break;
|
|
CASE_32_64(st16)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
*(uint16_t *)ptr = regs[r0];
|
|
break;
|
|
case INDEX_op_st_i32:
|
|
CASE_64(st32)
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
*(uint32_t *)ptr = regs[r0];
|
|
break;
|
|
|
|
/* Arithmetic operations (mixed 32/64 bit). */
|
|
|
|
CASE_32_64(add)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] + regs[r2];
|
|
break;
|
|
CASE_32_64(sub)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] - regs[r2];
|
|
break;
|
|
CASE_32_64(mul)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] * regs[r2];
|
|
break;
|
|
CASE_32_64(and)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] & regs[r2];
|
|
break;
|
|
CASE_32_64(or)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] | regs[r2];
|
|
break;
|
|
CASE_32_64(xor)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] ^ regs[r2];
|
|
break;
|
|
#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
|
|
CASE_32_64(andc)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] & ~regs[r2];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
|
|
CASE_32_64(orc)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] | ~regs[r2];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
|
|
CASE_32_64(eqv)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = ~(regs[r1] ^ regs[r2]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
|
|
CASE_32_64(nand)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = ~(regs[r1] & regs[r2]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
|
|
CASE_32_64(nor)
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = ~(regs[r1] | regs[r2]);
|
|
break;
|
|
#endif
|
|
|
|
/* Arithmetic operations (32 bit). */
|
|
|
|
case INDEX_op_div_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
|
|
break;
|
|
case INDEX_op_divu_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
|
|
break;
|
|
case INDEX_op_rem_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
|
|
break;
|
|
case INDEX_op_remu_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
|
|
break;
|
|
#if TCG_TARGET_HAS_clz_i32
|
|
case INDEX_op_clz_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
tmp32 = regs[r1];
|
|
regs[r0] = tmp32 ? clz32(tmp32) : regs[r2];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ctz_i32
|
|
case INDEX_op_ctz_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
tmp32 = regs[r1];
|
|
regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ctpop_i32
|
|
case INDEX_op_ctpop_i32:
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = ctpop32(regs[r1]);
|
|
break;
|
|
#endif
|
|
|
|
/* Shift/rotate operations (32 bit). */
|
|
|
|
case INDEX_op_shl_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
|
|
break;
|
|
case INDEX_op_shr_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
|
|
break;
|
|
case INDEX_op_sar_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
|
|
break;
|
|
#if TCG_TARGET_HAS_rot_i32
|
|
case INDEX_op_rotl_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = rol32(regs[r1], regs[r2] & 31);
|
|
break;
|
|
case INDEX_op_rotr_i32:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = ror32(regs[r1], regs[r2] & 31);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_deposit_i32
|
|
case INDEX_op_deposit_i32:
|
|
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
|
|
regs[r0] = deposit32(regs[r1], pos, len, regs[r2]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_extract_i32
|
|
case INDEX_op_extract_i32:
|
|
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
|
|
regs[r0] = extract32(regs[r1], pos, len);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_sextract_i32
|
|
case INDEX_op_sextract_i32:
|
|
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
|
|
regs[r0] = sextract32(regs[r1], pos, len);
|
|
break;
|
|
#endif
|
|
case INDEX_op_brcond_i32:
|
|
tci_args_rl(insn, tb_ptr, &r0, &ptr);
|
|
if ((uint32_t)regs[r0]) {
|
|
tb_ptr = ptr;
|
|
}
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
|
|
case INDEX_op_add2_i32:
|
|
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
|
|
T1 = tci_uint64(regs[r3], regs[r2]);
|
|
T2 = tci_uint64(regs[r5], regs[r4]);
|
|
tci_write_reg64(regs, r1, r0, T1 + T2);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
|
|
case INDEX_op_sub2_i32:
|
|
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
|
|
T1 = tci_uint64(regs[r3], regs[r2]);
|
|
T2 = tci_uint64(regs[r5], regs[r4]);
|
|
tci_write_reg64(regs, r1, r0, T1 - T2);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_mulu2_i32
|
|
case INDEX_op_mulu2_i32:
|
|
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
|
|
tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3];
|
|
tci_write_reg64(regs, r1, r0, tmp64);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_muls2_i32
|
|
case INDEX_op_muls2_i32:
|
|
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
|
|
tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3];
|
|
tci_write_reg64(regs, r1, r0, tmp64);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
|
|
CASE_32_64(ext8s)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = (int8_t)regs[r1];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
|
|
CASE_32_64(ext16s)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = (int16_t)regs[r1];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
|
|
CASE_32_64(ext8u)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = (uint8_t)regs[r1];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
|
|
CASE_32_64(ext16u)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = (uint16_t)regs[r1];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
|
|
CASE_32_64(bswap16)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = bswap16(regs[r1]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
|
|
CASE_32_64(bswap32)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = bswap32(regs[r1]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
|
|
CASE_32_64(not)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = ~regs[r1];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
|
|
CASE_32_64(neg)
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = -regs[r1];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
/* Load/store operations (64 bit). */
|
|
|
|
case INDEX_op_ld32s_i64:
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(int32_t *)ptr;
|
|
break;
|
|
case INDEX_op_ld_i64:
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
regs[r0] = *(uint64_t *)ptr;
|
|
break;
|
|
case INDEX_op_st_i64:
|
|
tci_args_rrs(insn, &r0, &r1, &ofs);
|
|
ptr = (void *)(regs[r1] + ofs);
|
|
*(uint64_t *)ptr = regs[r0];
|
|
break;
|
|
|
|
/* Arithmetic operations (64 bit). */
|
|
|
|
case INDEX_op_div_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
|
|
break;
|
|
case INDEX_op_divu_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
|
|
break;
|
|
case INDEX_op_rem_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
|
|
break;
|
|
case INDEX_op_remu_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
|
|
break;
|
|
#if TCG_TARGET_HAS_clz_i64
|
|
case INDEX_op_clz_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ctz_i64
|
|
case INDEX_op_ctz_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ctpop_i64
|
|
case INDEX_op_ctpop_i64:
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = ctpop64(regs[r1]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_mulu2_i64
|
|
case INDEX_op_mulu2_i64:
|
|
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
|
|
mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_muls2_i64
|
|
case INDEX_op_muls2_i64:
|
|
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
|
|
muls64(®s[r0], ®s[r1], regs[r2], regs[r3]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_add2_i64
|
|
case INDEX_op_add2_i64:
|
|
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
|
|
T1 = regs[r2] + regs[r4];
|
|
T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
|
|
regs[r0] = T1;
|
|
regs[r1] = T2;
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_add2_i64
|
|
case INDEX_op_sub2_i64:
|
|
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
|
|
T1 = regs[r2] - regs[r4];
|
|
T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
|
|
regs[r0] = T1;
|
|
regs[r1] = T2;
|
|
break;
|
|
#endif
|
|
|
|
/* Shift/rotate operations (64 bit). */
|
|
|
|
case INDEX_op_shl_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] << (regs[r2] & 63);
|
|
break;
|
|
case INDEX_op_shr_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = regs[r1] >> (regs[r2] & 63);
|
|
break;
|
|
case INDEX_op_sar_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
|
|
break;
|
|
#if TCG_TARGET_HAS_rot_i64
|
|
case INDEX_op_rotl_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = rol64(regs[r1], regs[r2] & 63);
|
|
break;
|
|
case INDEX_op_rotr_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
regs[r0] = ror64(regs[r1], regs[r2] & 63);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_deposit_i64
|
|
case INDEX_op_deposit_i64:
|
|
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
|
|
regs[r0] = deposit64(regs[r1], pos, len, regs[r2]);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_extract_i64
|
|
case INDEX_op_extract_i64:
|
|
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
|
|
regs[r0] = extract64(regs[r1], pos, len);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_sextract_i64
|
|
case INDEX_op_sextract_i64:
|
|
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
|
|
regs[r0] = sextract64(regs[r1], pos, len);
|
|
break;
|
|
#endif
|
|
case INDEX_op_brcond_i64:
|
|
tci_args_rl(insn, tb_ptr, &r0, &ptr);
|
|
if (regs[r0]) {
|
|
tb_ptr = ptr;
|
|
}
|
|
break;
|
|
case INDEX_op_ext32s_i64:
|
|
case INDEX_op_ext_i32_i64:
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = (int32_t)regs[r1];
|
|
break;
|
|
case INDEX_op_ext32u_i64:
|
|
case INDEX_op_extu_i32_i64:
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = (uint32_t)regs[r1];
|
|
break;
|
|
#if TCG_TARGET_HAS_bswap64_i64
|
|
case INDEX_op_bswap64_i64:
|
|
tci_args_rr(insn, &r0, &r1);
|
|
regs[r0] = bswap64(regs[r1]);
|
|
break;
|
|
#endif
|
|
#endif /* TCG_TARGET_REG_BITS == 64 */
|
|
|
|
/* QEMU specific operations. */
|
|
|
|
case INDEX_op_exit_tb:
|
|
tci_args_l(insn, tb_ptr, &ptr);
|
|
return (uintptr_t)ptr;
|
|
|
|
case INDEX_op_goto_tb:
|
|
tci_args_l(insn, tb_ptr, &ptr);
|
|
tb_ptr = *(void **)ptr;
|
|
break;
|
|
|
|
case INDEX_op_goto_ptr:
|
|
tci_args_r(insn, &r0);
|
|
ptr = (void *)regs[r0];
|
|
if (!ptr) {
|
|
return 0;
|
|
}
|
|
tb_ptr = ptr;
|
|
break;
|
|
|
|
case INDEX_op_qemu_ld_i32:
|
|
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
|
|
tci_args_rrm(insn, &r0, &r1, &oi);
|
|
taddr = regs[r1];
|
|
} else {
|
|
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
|
|
taddr = tci_uint64(regs[r2], regs[r1]);
|
|
}
|
|
tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
|
|
regs[r0] = tmp32;
|
|
break;
|
|
|
|
case INDEX_op_qemu_ld_i64:
|
|
if (TCG_TARGET_REG_BITS == 64) {
|
|
tci_args_rrm(insn, &r0, &r1, &oi);
|
|
taddr = regs[r1];
|
|
} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
|
|
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
|
|
taddr = regs[r2];
|
|
} else {
|
|
tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
|
|
taddr = tci_uint64(regs[r3], regs[r2]);
|
|
oi = regs[r4];
|
|
}
|
|
tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
|
|
if (TCG_TARGET_REG_BITS == 32) {
|
|
tci_write_reg64(regs, r1, r0, tmp64);
|
|
} else {
|
|
regs[r0] = tmp64;
|
|
}
|
|
break;
|
|
|
|
case INDEX_op_qemu_st_i32:
|
|
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
|
|
tci_args_rrm(insn, &r0, &r1, &oi);
|
|
taddr = regs[r1];
|
|
} else {
|
|
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
|
|
taddr = tci_uint64(regs[r2], regs[r1]);
|
|
}
|
|
tmp32 = regs[r0];
|
|
tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
|
|
break;
|
|
|
|
case INDEX_op_qemu_st_i64:
|
|
if (TCG_TARGET_REG_BITS == 64) {
|
|
tci_args_rrm(insn, &r0, &r1, &oi);
|
|
taddr = regs[r1];
|
|
tmp64 = regs[r0];
|
|
} else {
|
|
if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
|
|
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
|
|
taddr = regs[r2];
|
|
} else {
|
|
tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
|
|
taddr = tci_uint64(regs[r3], regs[r2]);
|
|
oi = regs[r4];
|
|
}
|
|
tmp64 = tci_uint64(regs[r1], regs[r0]);
|
|
}
|
|
tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
|
|
break;
|
|
|
|
case INDEX_op_mb:
|
|
/* Ensure ordering for all kinds */
|
|
smp_mb();
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Disassembler that matches the interpreter
|
|
*/
|
|
|
|
static const char *str_r(TCGReg r)
|
|
{
|
|
static const char regs[TCG_TARGET_NB_REGS][4] = {
|
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
|
"r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
|
|
};
|
|
|
|
QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14);
|
|
QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15);
|
|
|
|
assert((unsigned)r < TCG_TARGET_NB_REGS);
|
|
return regs[r];
|
|
}
|
|
|
|
static const char *str_c(TCGCond c)
|
|
{
|
|
static const char cond[16][8] = {
|
|
[TCG_COND_NEVER] = "never",
|
|
[TCG_COND_ALWAYS] = "always",
|
|
[TCG_COND_EQ] = "eq",
|
|
[TCG_COND_NE] = "ne",
|
|
[TCG_COND_LT] = "lt",
|
|
[TCG_COND_GE] = "ge",
|
|
[TCG_COND_LE] = "le",
|
|
[TCG_COND_GT] = "gt",
|
|
[TCG_COND_LTU] = "ltu",
|
|
[TCG_COND_GEU] = "geu",
|
|
[TCG_COND_LEU] = "leu",
|
|
[TCG_COND_GTU] = "gtu",
|
|
};
|
|
|
|
assert((unsigned)c < ARRAY_SIZE(cond));
|
|
assert(cond[c][0] != 0);
|
|
return cond[c];
|
|
}
|
|
|
|
/* Disassemble TCI bytecode. */
|
|
int print_insn_tci(bfd_vma addr, disassemble_info *info)
|
|
{
|
|
const uint32_t *tb_ptr = (const void *)(uintptr_t)addr;
|
|
const TCGOpDef *def;
|
|
const char *op_name;
|
|
uint32_t insn;
|
|
TCGOpcode op;
|
|
TCGReg r0, r1, r2, r3, r4, r5;
|
|
tcg_target_ulong i1;
|
|
int32_t s2;
|
|
TCGCond c;
|
|
TCGMemOpIdx oi;
|
|
uint8_t pos, len;
|
|
void *ptr;
|
|
|
|
/* TCI is always the host, so we don't need to load indirect. */
|
|
insn = *tb_ptr++;
|
|
|
|
info->fprintf_func(info->stream, "%08x ", insn);
|
|
|
|
op = extract32(insn, 0, 8);
|
|
def = &tcg_op_defs[op];
|
|
op_name = def->name;
|
|
|
|
switch (op) {
|
|
case INDEX_op_br:
|
|
case INDEX_op_exit_tb:
|
|
case INDEX_op_goto_tb:
|
|
tci_args_l(insn, tb_ptr, &ptr);
|
|
info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
|
|
break;
|
|
|
|
case INDEX_op_goto_ptr:
|
|
tci_args_r(insn, &r0);
|
|
info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0));
|
|
break;
|
|
|
|
case INDEX_op_call:
|
|
tci_args_nl(insn, tb_ptr, &len, &ptr);
|
|
info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr);
|
|
break;
|
|
|
|
case INDEX_op_brcond_i32:
|
|
case INDEX_op_brcond_i64:
|
|
tci_args_rl(insn, tb_ptr, &r0, &ptr);
|
|
info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p",
|
|
op_name, str_r(r0), ptr);
|
|
break;
|
|
|
|
case INDEX_op_setcond_i32:
|
|
case INDEX_op_setcond_i64:
|
|
tci_args_rrrc(insn, &r0, &r1, &r2, &c);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
|
|
op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
|
|
break;
|
|
|
|
case INDEX_op_tci_movi:
|
|
tci_args_ri(insn, &r0, &i1);
|
|
info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
|
|
op_name, str_r(r0), i1);
|
|
break;
|
|
|
|
case INDEX_op_tci_movl:
|
|
tci_args_rl(insn, tb_ptr, &r0, &ptr);
|
|
info->fprintf_func(info->stream, "%-12s %s, %p",
|
|
op_name, str_r(r0), ptr);
|
|
break;
|
|
|
|
case INDEX_op_ld8u_i32:
|
|
case INDEX_op_ld8u_i64:
|
|
case INDEX_op_ld8s_i32:
|
|
case INDEX_op_ld8s_i64:
|
|
case INDEX_op_ld16u_i32:
|
|
case INDEX_op_ld16u_i64:
|
|
case INDEX_op_ld16s_i32:
|
|
case INDEX_op_ld16s_i64:
|
|
case INDEX_op_ld32u_i64:
|
|
case INDEX_op_ld32s_i64:
|
|
case INDEX_op_ld_i32:
|
|
case INDEX_op_ld_i64:
|
|
case INDEX_op_st8_i32:
|
|
case INDEX_op_st8_i64:
|
|
case INDEX_op_st16_i32:
|
|
case INDEX_op_st16_i64:
|
|
case INDEX_op_st32_i64:
|
|
case INDEX_op_st_i32:
|
|
case INDEX_op_st_i64:
|
|
tci_args_rrs(insn, &r0, &r1, &s2);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %d",
|
|
op_name, str_r(r0), str_r(r1), s2);
|
|
break;
|
|
|
|
case INDEX_op_mov_i32:
|
|
case INDEX_op_mov_i64:
|
|
case INDEX_op_ext8s_i32:
|
|
case INDEX_op_ext8s_i64:
|
|
case INDEX_op_ext8u_i32:
|
|
case INDEX_op_ext8u_i64:
|
|
case INDEX_op_ext16s_i32:
|
|
case INDEX_op_ext16s_i64:
|
|
case INDEX_op_ext16u_i32:
|
|
case INDEX_op_ext32s_i64:
|
|
case INDEX_op_ext32u_i64:
|
|
case INDEX_op_ext_i32_i64:
|
|
case INDEX_op_extu_i32_i64:
|
|
case INDEX_op_bswap16_i32:
|
|
case INDEX_op_bswap16_i64:
|
|
case INDEX_op_bswap32_i32:
|
|
case INDEX_op_bswap32_i64:
|
|
case INDEX_op_bswap64_i64:
|
|
case INDEX_op_not_i32:
|
|
case INDEX_op_not_i64:
|
|
case INDEX_op_neg_i32:
|
|
case INDEX_op_neg_i64:
|
|
case INDEX_op_ctpop_i32:
|
|
case INDEX_op_ctpop_i64:
|
|
tci_args_rr(insn, &r0, &r1);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s",
|
|
op_name, str_r(r0), str_r(r1));
|
|
break;
|
|
|
|
case INDEX_op_add_i32:
|
|
case INDEX_op_add_i64:
|
|
case INDEX_op_sub_i32:
|
|
case INDEX_op_sub_i64:
|
|
case INDEX_op_mul_i32:
|
|
case INDEX_op_mul_i64:
|
|
case INDEX_op_and_i32:
|
|
case INDEX_op_and_i64:
|
|
case INDEX_op_or_i32:
|
|
case INDEX_op_or_i64:
|
|
case INDEX_op_xor_i32:
|
|
case INDEX_op_xor_i64:
|
|
case INDEX_op_andc_i32:
|
|
case INDEX_op_andc_i64:
|
|
case INDEX_op_orc_i32:
|
|
case INDEX_op_orc_i64:
|
|
case INDEX_op_eqv_i32:
|
|
case INDEX_op_eqv_i64:
|
|
case INDEX_op_nand_i32:
|
|
case INDEX_op_nand_i64:
|
|
case INDEX_op_nor_i32:
|
|
case INDEX_op_nor_i64:
|
|
case INDEX_op_div_i32:
|
|
case INDEX_op_div_i64:
|
|
case INDEX_op_rem_i32:
|
|
case INDEX_op_rem_i64:
|
|
case INDEX_op_divu_i32:
|
|
case INDEX_op_divu_i64:
|
|
case INDEX_op_remu_i32:
|
|
case INDEX_op_remu_i64:
|
|
case INDEX_op_shl_i32:
|
|
case INDEX_op_shl_i64:
|
|
case INDEX_op_shr_i32:
|
|
case INDEX_op_shr_i64:
|
|
case INDEX_op_sar_i32:
|
|
case INDEX_op_sar_i64:
|
|
case INDEX_op_rotl_i32:
|
|
case INDEX_op_rotl_i64:
|
|
case INDEX_op_rotr_i32:
|
|
case INDEX_op_rotr_i64:
|
|
case INDEX_op_clz_i32:
|
|
case INDEX_op_clz_i64:
|
|
case INDEX_op_ctz_i32:
|
|
case INDEX_op_ctz_i64:
|
|
tci_args_rrr(insn, &r0, &r1, &r2);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s",
|
|
op_name, str_r(r0), str_r(r1), str_r(r2));
|
|
break;
|
|
|
|
case INDEX_op_deposit_i32:
|
|
case INDEX_op_deposit_i64:
|
|
tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
|
|
op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
|
|
break;
|
|
|
|
case INDEX_op_extract_i32:
|
|
case INDEX_op_extract_i64:
|
|
case INDEX_op_sextract_i32:
|
|
case INDEX_op_sextract_i64:
|
|
tci_args_rrbb(insn, &r0, &r1, &pos, &len);
|
|
info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
|
|
op_name, str_r(r0), str_r(r1), pos, len);
|
|
break;
|
|
|
|
case INDEX_op_movcond_i32:
|
|
case INDEX_op_movcond_i64:
|
|
case INDEX_op_setcond2_i32:
|
|
tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
|
|
op_name, str_r(r0), str_r(r1), str_r(r2),
|
|
str_r(r3), str_r(r4), str_c(c));
|
|
break;
|
|
|
|
case INDEX_op_mulu2_i32:
|
|
case INDEX_op_mulu2_i64:
|
|
case INDEX_op_muls2_i32:
|
|
case INDEX_op_muls2_i64:
|
|
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
|
|
op_name, str_r(r0), str_r(r1),
|
|
str_r(r2), str_r(r3));
|
|
break;
|
|
|
|
case INDEX_op_add2_i32:
|
|
case INDEX_op_add2_i64:
|
|
case INDEX_op_sub2_i32:
|
|
case INDEX_op_sub2_i64:
|
|
tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
|
|
op_name, str_r(r0), str_r(r1), str_r(r2),
|
|
str_r(r3), str_r(r4), str_r(r5));
|
|
break;
|
|
|
|
case INDEX_op_qemu_ld_i64:
|
|
case INDEX_op_qemu_st_i64:
|
|
len = DIV_ROUND_UP(64, TCG_TARGET_REG_BITS);
|
|
goto do_qemu_ldst;
|
|
case INDEX_op_qemu_ld_i32:
|
|
case INDEX_op_qemu_st_i32:
|
|
len = 1;
|
|
do_qemu_ldst:
|
|
len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS);
|
|
switch (len) {
|
|
case 2:
|
|
tci_args_rrm(insn, &r0, &r1, &oi);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %x",
|
|
op_name, str_r(r0), str_r(r1), oi);
|
|
break;
|
|
case 3:
|
|
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x",
|
|
op_name, str_r(r0), str_r(r1), str_r(r2), oi);
|
|
break;
|
|
case 4:
|
|
tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
|
|
info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s",
|
|
op_name, str_r(r0), str_r(r1),
|
|
str_r(r2), str_r(r3), str_r(r4));
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
break;
|
|
|
|
case 0:
|
|
/* tcg_out_nop_fill uses zeros */
|
|
if (insn == 0) {
|
|
info->fprintf_func(info->stream, "align");
|
|
break;
|
|
}
|
|
/* fall through */
|
|
|
|
default:
|
|
info->fprintf_func(info->stream, "illegal opcode %d", op);
|
|
break;
|
|
}
|
|
|
|
return sizeof(insn);
|
|
}
|