8dcf525abc
As reported in http://article.gmane.org/gmane.comp.emulators.qemu/253987 Mac OSX actually requires describing all occupied slots in ACPI - even if hotplug isn't enabled. I didn't expect this so I dropped description of all non hotpluggable slots from ACPI. As a result: before commit99fd437dee(enable hotplug for pci bridges), PCI cards show up in the "device tree" of OS X (System Information). E.g., on MountainLion users have: Hardware -> PCI Cards: Card Type Driver Installed Slot *ethernet Ethernet Controller Yes PCI Slot 2 pci8086,2934 USB UHC Yes PCI Slot 29 ethernet: Type: Ethernet Controller Driver Installed: Yes MSI: No Bus: PCI Slot PCI Slot 2 Vendor ID: 0x8086 Device ID: 0x100e Subsystem Vendor ID: 0x1af4 Subsystem ID: 0x1100 Revision ID: 0x0003 Hardware -> Ethernet Cards ethernet: Type: Ethernet Controller Bus: PCI Slot PCI Slot 2 Vendor ID: 0x8086 Device ID: 0x100e Subsystem Vendor ID: 0x1af4 Subsystem ID: 0x1100 Revision ID: 0x0003 BSD name: en0 Kext name: AppleIntel8254XEthernet.kext Location: /System/Library/Extensions/... Version: 3.1.1b1 After commit99fd437dee, users get: Hardware -> PCI Cards: This computer doesn't contain any PCI cards. If you installed PCI cards, make sure they're properly installed. Hardware -> Ethernet Cards ethernet: Type: Ethernet Controller Bus: PCI Vendor ID: 0x8086 Device ID: 0x100e Subsystem Vendor ID: 0x1af4 Subsystem ID: 0x1100 Revision ID: 0x0003 BSD name: en0 Kext name: AppleIntel8254XEthernet.kext Location: /System/Library/Extensions/... Version: 3.1.1b1 Ethernet still works, but it's not showing up on the PCI bus, and it no longer thinks it's plugged in to slot #2, as it used to before the change. To fix, append description for all occupied non hotpluggable PCI slots. One need to be careful when doing this: VGA devices are now described in SSDT, so we need to drop description from DSDT. And ISA devices are used in DSDT so drop them from SSDT. Reported-by: Gabriel L. Somlo <gsomlo@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Also update generated dsdt and pcihp hex dump files. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
361 lines
11 KiB
Plaintext
361 lines
11 KiB
Plaintext
/*
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* Bochs/QEMU ACPI DSDT ASL definition
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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ACPI_EXTRACT_ALL_CODE AcpiDsdtAmlCode
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DefinitionBlock (
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"acpi-dsdt.aml", // Output Filename
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"DSDT", // Signature
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0x01, // DSDT Compliance Revision
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"BXPC", // OEMID
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"BXDSDT", // TABLE ID
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0x1 // OEM Revision
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)
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{
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#include "acpi-dsdt-dbug.dsl"
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/****************************************************************
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* PCI Bus definition
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****************************************************************/
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#define BOARD_SPECIFIC_PCI_RESOURSES \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0x0000, \
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0x0CF7, \
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0x0000, \
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0x0CF8, \
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,, , TypeStatic) \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0x0D00, \
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0xADFF, \
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0x0000, \
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0xA100, \
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,, , TypeStatic) \
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/* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0xAE0F, \
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0xAEFF, \
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0x0000, \
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0x00F1, \
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,, , TypeStatic) \
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/* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0xAF20, \
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0xAFDF, \
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0x0000, \
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0x00C0, \
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,, , TypeStatic) \
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/* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
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0x0000, \
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0xAFE4, \
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0xFFFF, \
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0x0000, \
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0x501C, \
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,, , TypeStatic)
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Scope(\_SB) {
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Device(PCI0) {
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Name(_HID, EisaId("PNP0A03"))
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Name(_ADR, 0x00)
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Name(_UID, 1)
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//#define PX13 S0B_
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// External(PX13, DeviceObj)
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}
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}
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#include "acpi-dsdt-pci-crs.dsl"
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#include "acpi-dsdt-hpet.dsl"
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/****************************************************************
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* PIIX4 PM
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****************************************************************/
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Scope(\_SB.PCI0) {
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Device(PX13) {
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Name(_ADR, 0x00010003)
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OperationRegion(P13C, PCI_Config, 0x00, 0xff)
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}
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}
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/****************************************************************
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* PIIX3 ISA bridge
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****************************************************************/
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Scope(\_SB.PCI0) {
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External(ISA, DeviceObj)
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Device(ISA) {
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Name(_ADR, 0x00010000)
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/* PIIX PCI to ISA irq remapping */
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OperationRegion(P40C, PCI_Config, 0x60, 0x04)
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/* enable bits */
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Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
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Offset(0x5f),
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, 7,
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LPEN, 1, // LPT
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Offset(0x67),
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, 3,
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CAEN, 1, // COM1
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, 3,
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CBEN, 1, // COM2
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}
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Name(FDEN, 1)
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}
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}
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#define DSDT_APPLESMC_STA piix_dsdt_applesmc_sta
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#include "acpi-dsdt-isa.dsl"
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/****************************************************************
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* PCI hotplug
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****************************************************************/
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Scope(\_SB.PCI0) {
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OperationRegion(PCST, SystemIO, 0xae00, 0x08)
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Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
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PCIU, 32,
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PCID, 32,
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}
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OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
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Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
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B0EJ, 32,
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}
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OperationRegion(BNMR, SystemIO, 0xae10, 0x04)
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Field(BNMR, DWordAcc, NoLock, WriteAsZeros) {
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BNUM, 32,
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}
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/* Lock to protect access to fields above. */
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Mutex(BLCK, 0)
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/* Methods called by bulk generated PCI devices below */
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/* Methods called by hotplug devices */
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Method(PCEJ, 2, NotSerialized) {
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// _EJ0 method - eject callback
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Acquire(BLCK, 0xFFFF)
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Store(Arg0, BNUM)
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Store(ShiftLeft(1, Arg1), B0EJ)
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Release(BLCK)
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Return (0x0)
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}
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/* Hotplug notification method supplied by SSDT */
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External(\_SB.PCI0.PCNT, MethodObj)
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}
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/****************************************************************
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* PCI IRQs
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****************************************************************/
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Scope(\_SB) {
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Scope(PCI0) {
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Name(_PRT, Package() {
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/* PCI IRQ routing table, example from ACPI 2.0a specification,
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section 6.2.8.1 */
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/* Note: we provide the same info as the PCI routing
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table of the Bochs BIOS */
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#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
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Package() { nr##ffff, 0, lnk0, 0 }, \
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Package() { nr##ffff, 1, lnk1, 0 }, \
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Package() { nr##ffff, 2, lnk2, 0 }, \
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Package() { nr##ffff, 3, lnk3, 0 }
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#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
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#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
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#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
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#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
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prt_slot0(0x0000),
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/* Device 1 is power mgmt device, and can only use irq 9 */
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prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
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prt_slot2(0x0002),
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prt_slot3(0x0003),
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prt_slot0(0x0004),
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prt_slot1(0x0005),
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prt_slot2(0x0006),
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prt_slot3(0x0007),
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prt_slot0(0x0008),
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prt_slot1(0x0009),
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prt_slot2(0x000a),
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prt_slot3(0x000b),
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prt_slot0(0x000c),
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prt_slot1(0x000d),
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prt_slot2(0x000e),
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prt_slot3(0x000f),
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prt_slot0(0x0010),
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prt_slot1(0x0011),
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prt_slot2(0x0012),
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prt_slot3(0x0013),
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prt_slot0(0x0014),
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prt_slot1(0x0015),
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prt_slot2(0x0016),
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prt_slot3(0x0017),
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prt_slot0(0x0018),
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prt_slot1(0x0019),
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prt_slot2(0x001a),
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prt_slot3(0x001b),
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prt_slot0(0x001c),
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prt_slot1(0x001d),
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prt_slot2(0x001e),
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prt_slot3(0x001f),
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})
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}
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Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
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PRQ0, 8,
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PRQ1, 8,
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PRQ2, 8,
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PRQ3, 8
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}
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Method(IQST, 1, NotSerialized) {
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// _STA method - get status
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If (And(0x80, Arg0)) {
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Return (0x09)
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}
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Return (0x0B)
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}
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Method(IQCR, 1, Serialized) {
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// _CRS method - get current settings
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Name(PRR0, ResourceTemplate() {
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Interrupt(, Level, ActiveHigh, Shared) { 0 }
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})
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CreateDWordField(PRR0, 0x05, PRRI)
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If (LLess(Arg0, 0x80)) {
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Store(Arg0, PRRI)
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}
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Return (PRR0)
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}
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#define define_link(link, uid, reg) \
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Device(link) { \
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Name(_HID, EISAID("PNP0C0F")) \
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Name(_UID, uid) \
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Name(_PRS, ResourceTemplate() { \
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Interrupt(, Level, ActiveHigh, Shared) { \
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5, 10, 11 \
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} \
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}) \
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Method(_STA, 0, NotSerialized) { \
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Return (IQST(reg)) \
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} \
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Method(_DIS, 0, NotSerialized) { \
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Or(reg, 0x80, reg) \
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} \
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Method(_CRS, 0, NotSerialized) { \
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Return (IQCR(reg)) \
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} \
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Method(_SRS, 1, NotSerialized) { \
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CreateDWordField(Arg0, 0x05, PRRI) \
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Store(PRRI, reg) \
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} \
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}
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define_link(LNKA, 0, PRQ0)
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define_link(LNKB, 1, PRQ1)
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define_link(LNKC, 2, PRQ2)
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define_link(LNKD, 3, PRQ3)
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Device(LNKS) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 4)
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Name(_PRS, ResourceTemplate() {
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Interrupt(, Level, ActiveHigh, Shared) { 9 }
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})
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// The SCI cannot be disabled and is always attached to GSI 9,
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// so these are no-ops. We only need this link to override the
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// polarity to active high and match the content of the MADT.
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Method(_STA, 0, NotSerialized) { Return (0x0b) }
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Method(_DIS, 0, NotSerialized) { }
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Method(_CRS, 0, NotSerialized) { Return (_PRS) }
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Method(_SRS, 1, NotSerialized) { }
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}
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}
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#include "hw/acpi/cpu_hotplug_defs.h"
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#define CPU_STATUS_BASE PIIX4_CPU_HOTPLUG_IO_BASE
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#include "acpi-dsdt-cpu-hotplug.dsl"
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/****************************************************************
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* General purpose events
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****************************************************************/
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Scope(\_GPE) {
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Name(_HID, "ACPI0006")
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Method(_L00) {
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}
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Method(_E01) {
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// PCI hotplug event
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Acquire(\_SB.PCI0.BLCK, 0xFFFF)
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\_SB.PCI0.PCNT()
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Release(\_SB.PCI0.BLCK)
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}
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Method(_E02) {
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// CPU hotplug event
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\_SB.PRSC()
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}
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Method(_L03) {
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}
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Method(_L04) {
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}
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Method(_L05) {
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}
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Method(_L06) {
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}
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Method(_L07) {
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}
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Method(_L08) {
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}
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Method(_L09) {
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}
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Method(_L0A) {
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}
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Method(_L0B) {
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}
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Method(_L0C) {
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}
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Method(_L0D) {
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}
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Method(_L0E) {
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}
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Method(_L0F) {
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}
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}
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}
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