79 lines
3.0 KiB
C
79 lines
3.0 KiB
C
/*
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* Header file for the Xilinx Versal's PMC IOU SLCR
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*
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* Copyright (C) 2021 Xilinx Inc
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This is a model of Xilinx Versal's PMC I/O Peripheral Control and Status
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* module documented in Versal's Technical Reference manual [1] and the Versal
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* ACAP Register reference [2].
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*
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* References:
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*
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* [1] Versal ACAP Technical Reference Manual,
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* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
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*
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* [2] Versal ACAP Register Reference,
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* https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html
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*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion for the device's registers
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* + sysbus IRQ 0: PMC (AXI and APB) parity error interrupt detected by the PMC
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* I/O peripherals.
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* + sysbus IRQ 1: Device interrupt.
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* + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
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* SD/eMMC controller 0.
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* + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
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* SD/eMMC controller 1.
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* + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
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* OSPI linear region.
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* + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
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* 1: OSPI direct access mode.
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*/
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#ifndef XLNX_VERSAL_PMC_IOU_SLCR_H
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#define XLNX_VERSAL_PMC_IOU_SLCR_H
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#include "hw/register.h"
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#define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalPmcIouSlcr, XILINX_VERSAL_PMC_IOU_SLCR)
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#define XILINX_VERSAL_PMC_IOU_SLCR_R_MAX (0x828 / 4 + 1)
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struct XlnxVersalPmcIouSlcr {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq_parity_imr;
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qemu_irq irq_imr;
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qemu_irq sd_emmc_sel[2];
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qemu_irq qspi_ospi_mux_sel;
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qemu_irq ospi_mux_sel;
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uint32_t regs[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];
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RegisterInfo regs_info[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];
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};
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#endif /* XLNX_VERSAL_PMC_IOU_SLCR_H */
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