302 lines
11 KiB
C
302 lines
11 KiB
C
/*
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* QEMU PowerPC XIVE internal structure definitions
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*
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*
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* The XIVE structures are accessed by the HW and their format is
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* architected to be big-endian. Some macros are provided to ease
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* access to the different fields.
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*
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*
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* Copyright (c) 2016-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_XIVE_REGS_H
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#define PPC_XIVE_REGS_H
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#include "qemu/bswap.h"
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#include "qemu/host-utils.h"
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/*
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* Interrupt source number encoding on PowerBUS
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*/
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/*
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* Trigger data definition
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*
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* The trigger definition is used for triggers both for HW source
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* interrupts (PHB, PSI), as well as for rerouting interrupts between
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* Interrupt Controller.
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*
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* HW source controllers set bit0 of word0 to ‘0’ as they provide EAS
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* information (EAS block + EAS index) in the 8 byte data and not END
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* information, which is use for rerouting interrupts.
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*
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* bit1 of word0 to ‘1’ signals that the state bit check has been
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* performed.
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*/
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#define XIVE_TRIGGER_END PPC_BIT(0)
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#define XIVE_TRIGGER_PQ PPC_BIT(1)
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/*
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* QEMU macros to manipulate the trigger payload in native endian
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*/
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#define XIVE_EAS_BLOCK(n) (((n) >> 28) & 0xf)
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#define XIVE_EAS_INDEX(n) ((n) & 0x0fffffff)
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#define XIVE_EAS(blk, idx) ((uint32_t)(blk) << 28 | (idx))
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#define TM_SHIFT 16
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/* TM register offsets */
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#define TM_QW0_USER 0x000 /* All rings */
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#define TM_QW1_OS 0x010 /* Ring 0..2 */
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#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
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#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
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/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */
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#define TM_NSR 0x0 /* + + - + */
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#define TM_CPPR 0x1 /* - + - + */
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#define TM_IPB 0x2 /* - + + + */
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#define TM_LSMFB 0x3 /* - + + + */
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#define TM_ACK_CNT 0x4 /* - + - - */
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#define TM_INC 0x5 /* - + - + */
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#define TM_AGE 0x6 /* - + - + */
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#define TM_PIPR 0x7 /* - + - + */
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#define TM_WORD0 0x0
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#define TM_WORD1 0x4
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/*
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* QW word 2 contains the valid bit at the top and other fields
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* depending on the QW.
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*/
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#define TM_WORD2 0x8
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#define TM_QW0W2_VU PPC_BIT32(0)
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#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
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#define TM_QW1W2_VO PPC_BIT32(0)
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#define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31)
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#define TM_QW2W2_VP PPC_BIT32(0)
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#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31)
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#define TM_QW3W2_VT PPC_BIT32(0)
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#define TM_QW3W2_LP PPC_BIT32(6)
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#define TM_QW3W2_LE PPC_BIT32(7)
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#define TM_QW3W2_T PPC_BIT32(31)
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/*
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* In addition to normal loads to "peek" and writes (only when invalid)
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* using 4 and 8 bytes accesses, the above registers support these
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* "special" byte operations:
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*
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* - Byte load from QW0[NSR] - User level NSR (EBB)
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* - Byte store to QW0[NSR] - User level NSR (EBB)
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* - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
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* - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
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* otherwise VT||0000000
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* - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
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*
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* Then we have all these "special" CI ops at these offset that trigger
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* all sorts of side effects:
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*/
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
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#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user
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* context */
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#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
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#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS
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* context to reg */
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#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool
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* context to reg*/
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#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
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#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd
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* line */
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#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
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#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even
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* line */
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#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
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/* XXX more... */
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/* NSR fields for the various QW ack types */
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#define TM_QW0_NSR_EB PPC_BIT8(0)
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#define TM_QW1_NSR_EO PPC_BIT8(0)
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#define TM_QW3_NSR_HE PPC_BITMASK8(0, 1)
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#define TM_QW3_NSR_HE_NONE 0
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#define TM_QW3_NSR_HE_POOL 1
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#define TM_QW3_NSR_HE_PHYS 2
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#define TM_QW3_NSR_HE_LSI 3
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#define TM_QW3_NSR_I PPC_BIT8(2)
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#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3, 7)
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/*
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* EAS (Event Assignment Structure)
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*
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* One per interrupt source. Targets an interrupt to a given Event
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* Notification Descriptor (END) and provides the corresponding
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* logical interrupt number (END data)
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*/
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typedef struct XiveEAS {
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/*
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* Use a single 64-bit definition to make it easier to perform
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* atomic updates
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*/
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uint64_t w;
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#define EAS_VALID PPC_BIT(0)
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#define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
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#define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */
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#define EAS_MASKED PPC_BIT(32) /* Masked */
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#define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */
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} XiveEAS;
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#define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID)
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#define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED)
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void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
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static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
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{
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return (be64_to_cpu(word) & mask) >> ctz64(mask);
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}
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static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word,
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uint64_t value)
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{
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uint64_t tmp =
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(be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask);
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return cpu_to_be64(tmp);
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}
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static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word)
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{
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return (be32_to_cpu(word) & mask) >> ctz32(mask);
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}
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static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word,
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uint32_t value)
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{
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uint32_t tmp =
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(be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask);
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return cpu_to_be32(tmp);
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}
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/* Event Notification Descriptor (END) */
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typedef struct XiveEND {
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uint32_t w0;
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#define END_W0_VALID PPC_BIT32(0) /* "v" bit */
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#define END_W0_ENQUEUE PPC_BIT32(1) /* "q" bit */
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#define END_W0_UCOND_NOTIFY PPC_BIT32(2) /* "n" bit */
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#define END_W0_BACKLOG PPC_BIT32(3) /* "b" bit */
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#define END_W0_PRECL_ESC_CTL PPC_BIT32(4) /* "p" bit */
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#define END_W0_ESCALATE_CTL PPC_BIT32(5) /* "e" bit */
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#define END_W0_UNCOND_ESCALATE PPC_BIT32(6) /* "u" bit - DD2.0 */
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#define END_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit - DD2.0 */
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#define END_W0_QSIZE PPC_BITMASK32(12, 15)
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#define END_W0_SW0 PPC_BIT32(16)
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#define END_W0_FIRMWARE END_W0_SW0 /* Owned by FW */
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#define END_QSIZE_4K 0
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#define END_QSIZE_64K 4
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#define END_W0_HWDEP PPC_BITMASK32(24, 31)
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uint32_t w1;
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#define END_W1_ESn PPC_BITMASK32(0, 1)
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#define END_W1_ESn_P PPC_BIT32(0)
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#define END_W1_ESn_Q PPC_BIT32(1)
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#define END_W1_ESe PPC_BITMASK32(2, 3)
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#define END_W1_ESe_P PPC_BIT32(2)
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#define END_W1_ESe_Q PPC_BIT32(3)
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#define END_W1_GENERATION PPC_BIT32(9)
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#define END_W1_PAGE_OFF PPC_BITMASK32(10, 31)
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uint32_t w2;
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#define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3)
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#define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31)
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uint32_t w3;
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#define END_W3_OP_DESC_LO PPC_BITMASK32(0, 31)
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uint32_t w4;
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#define END_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7)
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#define END_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
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uint32_t w5;
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#define END_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
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uint32_t w6;
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#define END_W6_FORMAT_BIT PPC_BIT32(8)
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#define END_W6_NVT_BLOCK PPC_BITMASK32(9, 12)
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#define END_W6_NVT_INDEX PPC_BITMASK32(13, 31)
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uint32_t w7;
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#define END_W7_F0_IGNORE PPC_BIT32(0)
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#define END_W7_F0_BLK_GROUPING PPC_BIT32(1)
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#define END_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
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#define END_W7_F1_WAKEZ PPC_BIT32(0)
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#define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31)
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} XiveEND;
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#define xive_end_is_valid(end) (be32_to_cpu((end)->w0) & END_W0_VALID)
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#define xive_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
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#define xive_end_is_notify(end) (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
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#define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
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#define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
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#define xive_end_is_uncond_escalation(end) \
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(be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
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#define xive_end_is_silent_escalation(end) \
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(be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
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#define xive_end_is_firmware(end) \
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(be32_to_cpu((end)->w0) & END_W0_FIRMWARE)
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static inline uint64_t xive_end_qaddr(XiveEND *end)
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{
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return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 |
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be32_to_cpu(end->w3);
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}
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void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
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void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
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void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
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/* Notification Virtual Target (NVT) */
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typedef struct XiveNVT {
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uint32_t w0;
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#define NVT_W0_VALID PPC_BIT32(0)
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uint32_t w1;
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#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3)
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#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31)
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uint32_t w2;
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uint32_t w3;
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uint32_t w4;
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#define NVT_W4_IPB PPC_BITMASK32(16, 23)
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uint32_t w5;
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uint32_t w6;
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uint32_t w7;
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uint32_t w8;
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#define NVT_W8_GRP_VALID PPC_BIT32(0)
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uint32_t w9;
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uint32_t wa;
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uint32_t wb;
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uint32_t wc;
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uint32_t wd;
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uint32_t we;
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uint32_t wf;
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} XiveNVT;
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#define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
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/*
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* The VP number space in a block is defined by the END_W6_NVT_INDEX
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* field of the XIVE END
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*/
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#define XIVE_NVT_SHIFT 19
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#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT)
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static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
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{
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return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx;
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}
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static inline uint32_t xive_nvt_idx(uint32_t cam_line)
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{
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return cam_line & ((1 << XIVE_NVT_SHIFT) - 1);
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}
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static inline uint32_t xive_nvt_blk(uint32_t cam_line)
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{
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return (cam_line >> XIVE_NVT_SHIFT) & 0xf;
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}
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#endif /* PPC_XIVE_REGS_H */
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