7d378ed6e3
The watchdog is part of NPCM7XX's timer module. Its behavior is controlled by the WTCR register in the timer. When enabled, the watchdog issues an interrupt signal after a pre-set amount of cycles, and issues a reset signal shortly after that. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: deleted blank line at end of npcm_watchdog_timer-test.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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a9gtimer.h | ||
allwinner-a10-pit.h | ||
arm_mptimer.h | ||
armv7m_systick.h | ||
aspeed_timer.h | ||
avr_timer16.h | ||
bcm2835_systmr.h | ||
cmsdk-apb-dualtimer.h | ||
cmsdk-apb-timer.h | ||
digic-timer.h | ||
hpet.h | ||
i8254_internal.h | ||
i8254.h | ||
imx_epit.h | ||
imx_gpt.h | ||
mips_gictimer.h | ||
mss-timer.h | ||
npcm7xx_timer.h | ||
nrf51_timer.h | ||
renesas_cmt.h | ||
renesas_tmr.h | ||
stm32f2xx_timer.h | ||
tmu012.h |