Alex Richardson 529577457c target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR ... The TW and TSR fields should be bits 21 and 22 and not 30/29. This was found while comparing QEMU behaviour against the sail formal model (https://github.com/rems-project/sail-riscv/). Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-12-17 21:56:43 -08:00
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insn_trans	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
cpu_bits.h	target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR	2020-12-17 21:56:43 -08:00
cpu_helper.c	target/riscv: Fix the bug of HLVX/HLV/HSV	2020-12-17 21:56:43 -08:00
cpu_user.h
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
cpu.h	target/riscv: Remove the hyp load and store functions	2020-11-09 15:08:57 -08:00
csr.c	target/riscv/csr.c : add space before the open parenthesis '('	2020-11-03 07:17:23 -08:00
fpu_helper.c
gdbstub.c
helper.h	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Add V extension state description	2020-11-03 07:17:23 -08:00
meson.build	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
pmp.c	target/riscv: Add PMP state description	2020-11-03 07:17:23 -08:00
pmp.h	target/riscv: Add PMP state description	2020-11-03 07:17:23 -08:00
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h
translate.c	target/riscv: Remove the hyp load and store functions	2020-11-09 15:08:57 -08:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00