Peter Maydell 52ff951b4f target-arm: Add comment about not implementing NSACR.RFR ... QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org		2016-02-26 15:09:41 +00:00
..
arch_dump.c
arm_ldst.h
arm-semi.c
cpu64.c	target-arm: Add the pmceid0 and pmceid1 registers	2016-02-18 14:16:17 +00:00
cpu-qom.h	target-arm: Add the pmceid0 and pmceid1 registers	2016-02-18 14:16:17 +00:00
cpu.c	target-arm: Add the pmceid0 and pmceid1 registers	2016-02-18 14:16:17 +00:00
cpu.h	target-arm: Add write_type argument to cpsr_write()	2016-02-26 15:09:41 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c	target-arm: Add write_type argument to cpsr_write()	2016-02-26 15:09:41 +00:00
helper-a64.c
helper-a64.h
helper.c	target-arm: Add comment about not implementing NSACR.RFR	2016-02-26 15:09:41 +00:00
helper.h	target-arm: Give CPSR setting on 32-bit exception return its own helper	2016-02-26 15:09:41 +00:00
internals.h
iwmmxt_helper.c
kvm32.c	target-arm: Add write_type argument to cpsr_write()	2016-02-26 15:09:41 +00:00
kvm64.c	target-arm: Raw CPSR writes should skip checks and bank switching	2016-02-26 15:09:41 +00:00
kvm_arm.h
kvm-consts.h	all: Clean up includes	2016-02-23 12:43:05 +00:00
kvm-stub.c
kvm.c
machine.c	target-arm: Raw CPSR writes should skip checks and bank switching	2016-02-26 15:09:41 +00:00
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c	target-arm: Raw CPSR writes should skip checks and bank switching	2016-02-26 15:09:41 +00:00
psci.c
translate-a64.c
translate.c	target-arm: Give CPSR setting on 32-bit exception return its own helper	2016-02-26 15:09:41 +00:00
translate.h