5373c61d6a
The TIMA region gives access to the thread interrupt context registers of a CPU. It is mapped at the same address on all chips and can be accessed by any CPU of the system. To identify the chip from which the access is being done, the PowerBUS uses a 'chip' field in the load/store messages. QEMU does not model these messages, instead, we extract the chip id from the CPU PIR and do a lookup at the machine level to fetch the targeted interrupt controller. Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify this process in pnv_xive_get_tctx(). The latter will be removed in the subsequent patches but the same principle will be kept. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191125065820.927-14-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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| .. | ||
| fdt.h | ||
| mac_dbdma.h | ||
| openpic_kvm.h | ||
| openpic.h | ||
| pnv_core.h | ||
| pnv_homer.h | ||
| pnv_lpc.h | ||
| pnv_occ.h | ||
| pnv_pnor.h | ||
| pnv_psi.h | ||
| pnv_xive.h | ||
| pnv_xscom.h | ||
| pnv.h | ||
| ppc4xx.h | ||
| ppc_e500.h | ||
| ppc.h | ||
| spapr_cpu_core.h | ||
| spapr_drc.h | ||
| spapr_irq.h | ||
| spapr_ovec.h | ||
| spapr_rtas.h | ||
| spapr_tpm_proxy.h | ||
| spapr_vio.h | ||
| spapr_xive.h | ||
| spapr.h | ||
| xics_spapr.h | ||
| xics.h | ||
| xive_regs.h | ||
| xive.h | ||