OpenE2K/qemu-e2k
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qemu-e2k/target/riscv
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Kito Cheng dd205025a0 softfloat: Implement the full set of comparisons for float16 
Implement them in softfloat and remove the local versions in riscv.

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596102747-20226-2-git-send-email-chihmin.chao@sifive.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-08-28 10:48:07 -07:00
..
insn_trans target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
cpu_bits.h target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
cpu_helper.c target/riscv: Update the Hypervisor trap return/entry 2020-08-25 09:11:36 -07:00
cpu_user.h
cpu-param.h
cpu.c target/riscv: configure and turn on vector extension from command line 2020-07-02 09:19:34 -07:00
cpu.h target/riscv: Allow setting a two-stage lookup in the virt status 2020-08-25 09:11:35 -07:00
csr.c target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
fpu_helper.c target/riscv: Check nanboxed inputs to fp helpers 2020-08-21 22:37:55 -07:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.h target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
insn32.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
instmap.h
internals.h target/riscv: Check nanboxed inputs to fp helpers 2020-08-21 22:37:55 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
monitor.c target/riscv: Drop support for ISA spec version 1.09.1 2020-06-03 09:11:51 -07:00
op_helper.c target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
pmp.c target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
pmp.h target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
trace-events
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Update the Hypervisor trap return/entry 2020-08-25 09:11:36 -07:00
vector_helper.c softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00