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53a72dfda5
qemu-e2k/target-xtensa
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Max Filippov 53a72dfda5 target-xtensa: mask out undefined bits of WINDOWSTART SR 
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SR
must be zero.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02 05:05:38 +04:00
..
core-dc232b target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
core-dc232b.c target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf.c target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
cpu.h target-xtensa: extract core configuration from overlay 2011-10-16 10:39:52 +00:00
helper.c target-xtensa: extract core configuration from overlay 2011-10-16 10:39:52 +00:00
helpers.h
machine.c
op_helper.c
overlay_tool.h target-xtensa: extract core configuration from overlay 2011-10-16 10:39:52 +00:00
translate.c target-xtensa: mask out undefined bits of WINDOWSTART SR 2011-11-02 05:05:38 +04:00