1005 lines
26 KiB
C
1005 lines
26 KiB
C
/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "msix.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "kvm.h"
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//#define DEBUG_APIC
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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#define APIC_LVT_NB 6
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_SMI 2
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#define APIC_DM_NMI 4
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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/* APIC destination mode */
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#define APIC_DESTMODE_FLAT 0xf
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#define APIC_DESTMODE_CLUSTER 1
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#define APIC_TRIGGER_EDGE 0
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#define APIC_TRIGGER_LEVEL 1
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#define APIC_LVT_TIMER_PERIODIC (1<<17)
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#define APIC_LVT_MASKED (1<<16)
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#define APIC_LVT_LEVEL_TRIGGER (1<<15)
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#define APIC_LVT_REMOTE_IRR (1<<14)
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#define APIC_INPUT_POLARITY (1<<13)
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#define APIC_SEND_PENDING (1<<12)
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#define ESR_ILLEGAL_ADDRESS (1 << 7)
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#define APIC_SV_ENABLE (1 << 8)
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#define MAX_APICS 255
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#define MAX_APIC_WORDS 8
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/* Intel APIC constants: from include/asm/msidef.h */
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#define MSI_DATA_VECTOR_SHIFT 0
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#define MSI_DATA_VECTOR_MASK 0x000000ff
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8
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#define MSI_DATA_TRIGGER_SHIFT 15
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#define MSI_DATA_LEVEL_SHIFT 14
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#define MSI_ADDR_DEST_MODE_SHIFT 2
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#define MSI_ADDR_DEST_ID_SHIFT 12
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
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#define MSI_ADDR_BASE 0xfee00000
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#define MSI_ADDR_SIZE 0x100000
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typedef struct APICState {
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CPUState *cpu_env;
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uint32_t apicbase;
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uint8_t id;
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uint8_t arb_id;
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uint8_t tpr;
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uint32_t spurious_vec;
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uint8_t log_dest;
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uint8_t dest_mode;
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uint32_t isr[8]; /* in service register */
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uint32_t tmr[8]; /* trigger mode register */
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uint32_t irr[8]; /* interrupt request register */
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uint32_t lvt[APIC_LVT_NB];
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uint32_t esr; /* error register */
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uint32_t icr[2];
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uint32_t divide_conf;
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int count_shift;
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uint32_t initial_count;
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int64_t initial_count_load_time, next_time;
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uint32_t idx;
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QEMUTimer *timer;
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int sipi_vector;
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int wait_for_sipi;
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} APICState;
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static int apic_io_memory;
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static APICState *local_apics[MAX_APICS + 1];
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static int last_apic_idx = 0;
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static int apic_irq_delivered;
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICState *s);
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode);
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value)
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{
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return 31 - clz32(value);
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}
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/* Find first bit starting from lsb */
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static int ffs_bit(uint32_t value)
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{
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return ctz32(value);
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}
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static inline void set_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] |= mask;
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}
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static inline void reset_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] &= ~mask;
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}
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static inline int get_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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return !!(tab[i] & mask);
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}
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static void apic_local_deliver(CPUState *env, int vector)
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{
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APICState *s = env->apic_state;
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uint32_t lvt = s->lvt[vector];
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int trigger_mode;
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) {
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case APIC_DM_SMI:
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cpu_interrupt(env, CPU_INTERRUPT_SMI);
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break;
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case APIC_DM_NMI:
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cpu_interrupt(env, CPU_INTERRUPT_NMI);
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break;
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case APIC_DM_EXTINT:
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE;
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER))
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trigger_mode = APIC_TRIGGER_LEVEL;
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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}
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}
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void apic_deliver_pic_intr(CPUState *env, int level)
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{
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if (level)
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apic_local_deliver(env, APIC_LVT_LINT0);
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else {
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APICState *s = env->apic_state;
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uint32_t lvt = s->lvt[APIC_LVT_LINT0];
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switch ((lvt >> 8) & 7) {
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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break;
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}
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}
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}
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
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__mask = deliver_bitmask[__i];\
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\
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if (__mask & (1 << __j)) {\
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\
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}\
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}\
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}\
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}\
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}\
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}
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static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode)
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{
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APICState *apic_iter;
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) {
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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}
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}
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if (d >= 0) {
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apic_iter = local_apics[d];
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode);
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}
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}
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}
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return;
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case APIC_DM_FIXED:
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break;
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
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return;
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case APIC_DM_NMI:
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
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return;
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
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return;
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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default:
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return;
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_set_irq(apic_iter, vector_num, trigger_mode) );
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}
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t polarity, uint8_t trigger_mode)
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{
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
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trigger_mode);
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}
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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{
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APICState *s = env->apic_state;
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#ifdef DEBUG_APIC
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printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
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#endif
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if (!s)
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return;
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
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env->cpuid_features &= ~CPUID_APIC;
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s->spurious_vec &= ~APIC_SV_ENABLE;
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}
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}
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uint64_t cpu_get_apic_base(CPUState *env)
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{
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APICState *s = env->apic_state;
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#ifdef DEBUG_APIC
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printf("cpu_get_apic_base: %016" PRIx64 "\n",
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s ? (uint64_t)s->apicbase: 0);
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#endif
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return s ? s->apicbase : 0;
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}
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void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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{
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APICState *s = env->apic_state;
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if (!s)
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return;
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s->tpr = (val & 0x0f) << 4;
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apic_update_irq(s);
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}
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uint8_t cpu_get_apic_tpr(CPUX86State *env)
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{
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APICState *s = env->apic_state;
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return s ? s->tpr >> 4 : 0;
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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{
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int i;
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for(i = 7; i >= 0; i--) {
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if (tab[i] != 0) {
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return i * 32 + fls_bit(tab[i]);
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}
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}
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return -1;
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}
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static int apic_get_ppr(APICState *s)
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{
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int tpr, isrv, ppr;
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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isrv = 0;
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isrv >>= 4;
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if (tpr >= isrv)
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ppr = s->tpr;
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else
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ppr = isrv << 4;
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return ppr;
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}
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static int apic_get_arb_pri(APICState *s)
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{
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/* XXX: arbitration */
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return 0;
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}
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/* signal the CPU if an irq is pending */
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static void apic_update_irq(APICState *s)
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{
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int irrv, ppr;
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if (!(s->spurious_vec & APIC_SV_ENABLE))
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return;
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irrv = get_highest_priority_int(s->irr);
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if (irrv < 0)
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return;
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ppr = apic_get_ppr(s);
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if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
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return;
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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}
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void apic_reset_irq_delivered(void)
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{
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apic_irq_delivered = 0;
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}
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int apic_get_irq_delivered(void)
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{
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return apic_irq_delivered;
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}
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
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{
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apic_irq_delivered += !get_bit(s->irr, vector_num);
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set_bit(s->irr, vector_num);
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if (trigger_mode)
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set_bit(s->tmr, vector_num);
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else
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reset_bit(s->tmr, vector_num);
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apic_update_irq(s);
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}
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static void apic_eoi(APICState *s)
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{
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int isrv;
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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return;
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reset_bit(s->isr, isrv);
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/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
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set the remote IRR bit for level triggered interrupts. */
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apic_update_irq(s);
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}
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static int apic_find_dest(uint8_t dest)
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{
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APICState *apic = local_apics[dest];
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int i;
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if (apic && apic->id == dest)
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return dest; /* shortcut in case apic->id == apic->idx */
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for (i = 0; i < MAX_APICS; i++) {
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apic = local_apics[i];
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if (apic && apic->id == dest)
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return i;
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}
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return -1;
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}
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode)
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{
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APICState *apic_iter;
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int i;
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if (dest_mode == 0) {
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if (dest == 0xff) {
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memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
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} else {
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int idx = apic_find_dest(dest);
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
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if (idx >= 0)
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set_bit(deliver_bitmask, idx);
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}
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} else {
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/* XXX: cluster mode */
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
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for(i = 0; i < MAX_APICS; i++) {
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apic_iter = local_apics[i];
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if (apic_iter) {
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if (apic_iter->dest_mode == 0xf) {
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if (dest & apic_iter->log_dest)
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set_bit(deliver_bitmask, i);
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} else if (apic_iter->dest_mode == 0x0) {
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if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
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(dest & apic_iter->log_dest & 0x0f)) {
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set_bit(deliver_bitmask, i);
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}
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}
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}
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}
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}
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}
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void apic_init_reset(CPUState *env)
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{
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APICState *s = env->apic_state;
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int i;
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if (!s)
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return;
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s->tpr = 0;
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s->spurious_vec = 0xff;
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s->log_dest = 0;
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s->dest_mode = 0xf;
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memset(s->isr, 0, sizeof(s->isr));
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memset(s->tmr, 0, sizeof(s->tmr));
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memset(s->irr, 0, sizeof(s->irr));
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for(i = 0; i < APIC_LVT_NB; i++)
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s->lvt[i] = 1 << 16; /* mask LVT */
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s->esr = 0;
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memset(s->icr, 0, sizeof(s->icr));
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s->divide_conf = 0;
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s->count_shift = 0;
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s->initial_count = 0;
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s->initial_count_load_time = 0;
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s->next_time = 0;
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s->wait_for_sipi = 1;
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env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
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}
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static void apic_startup(APICState *s, int vector_num)
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{
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s->sipi_vector = vector_num;
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
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}
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void apic_sipi(CPUState *env)
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{
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APICState *s = env->apic_state;
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cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI);
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|
|
|
if (!s->wait_for_sipi)
|
|
return;
|
|
|
|
env->eip = 0;
|
|
cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
|
|
0xffff, 0);
|
|
env->halted = 0;
|
|
s->wait_for_sipi = 0;
|
|
}
|
|
|
|
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
|
|
uint8_t delivery_mode, uint8_t vector_num,
|
|
uint8_t polarity, uint8_t trigger_mode)
|
|
{
|
|
uint32_t deliver_bitmask[MAX_APIC_WORDS];
|
|
int dest_shorthand = (s->icr[0] >> 18) & 3;
|
|
APICState *apic_iter;
|
|
|
|
switch (dest_shorthand) {
|
|
case 0:
|
|
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
|
|
break;
|
|
case 1:
|
|
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
|
|
set_bit(deliver_bitmask, s->idx);
|
|
break;
|
|
case 2:
|
|
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
|
|
break;
|
|
case 3:
|
|
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
|
|
reset_bit(deliver_bitmask, s->idx);
|
|
break;
|
|
}
|
|
|
|
switch (delivery_mode) {
|
|
case APIC_DM_INIT:
|
|
{
|
|
int trig_mode = (s->icr[0] >> 15) & 1;
|
|
int level = (s->icr[0] >> 14) & 1;
|
|
if (level == 0 && trig_mode == 1) {
|
|
foreach_apic(apic_iter, deliver_bitmask,
|
|
apic_iter->arb_id = apic_iter->id );
|
|
return;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case APIC_DM_SIPI:
|
|
foreach_apic(apic_iter, deliver_bitmask,
|
|
apic_startup(apic_iter, vector_num) );
|
|
return;
|
|
}
|
|
|
|
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
|
|
trigger_mode);
|
|
}
|
|
|
|
int apic_get_interrupt(CPUState *env)
|
|
{
|
|
APICState *s = env->apic_state;
|
|
int intno;
|
|
|
|
/* if the APIC is installed or enabled, we let the 8259 handle the
|
|
IRQs */
|
|
if (!s)
|
|
return -1;
|
|
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
|
return -1;
|
|
|
|
/* XXX: spurious IRQ handling */
|
|
intno = get_highest_priority_int(s->irr);
|
|
if (intno < 0)
|
|
return -1;
|
|
if (s->tpr && intno <= s->tpr)
|
|
return s->spurious_vec & 0xff;
|
|
reset_bit(s->irr, intno);
|
|
set_bit(s->isr, intno);
|
|
apic_update_irq(s);
|
|
return intno;
|
|
}
|
|
|
|
int apic_accept_pic_intr(CPUState *env)
|
|
{
|
|
APICState *s = env->apic_state;
|
|
uint32_t lvt0;
|
|
|
|
if (!s)
|
|
return -1;
|
|
|
|
lvt0 = s->lvt[APIC_LVT_LINT0];
|
|
|
|
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
|
|
(lvt0 & APIC_LVT_MASKED) == 0)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t apic_get_current_count(APICState *s)
|
|
{
|
|
int64_t d;
|
|
uint32_t val;
|
|
d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
|
|
s->count_shift;
|
|
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
|
/* periodic */
|
|
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
|
} else {
|
|
if (d >= s->initial_count)
|
|
val = 0;
|
|
else
|
|
val = s->initial_count - d;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static void apic_timer_update(APICState *s, int64_t current_time)
|
|
{
|
|
int64_t next_time, d;
|
|
|
|
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
|
d = (current_time - s->initial_count_load_time) >>
|
|
s->count_shift;
|
|
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
|
if (!s->initial_count)
|
|
goto no_timer;
|
|
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
|
|
} else {
|
|
if (d >= s->initial_count)
|
|
goto no_timer;
|
|
d = (uint64_t)s->initial_count + 1;
|
|
}
|
|
next_time = s->initial_count_load_time + (d << s->count_shift);
|
|
qemu_mod_timer(s->timer, next_time);
|
|
s->next_time = next_time;
|
|
} else {
|
|
no_timer:
|
|
qemu_del_timer(s->timer);
|
|
}
|
|
}
|
|
|
|
static void apic_timer(void *opaque)
|
|
{
|
|
APICState *s = opaque;
|
|
|
|
apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
|
|
apic_timer_update(s, s->next_time);
|
|
}
|
|
|
|
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
}
|
|
|
|
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
}
|
|
|
|
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
CPUState *env;
|
|
APICState *s;
|
|
uint32_t val;
|
|
int index;
|
|
|
|
env = cpu_single_env;
|
|
if (!env)
|
|
return 0;
|
|
s = env->apic_state;
|
|
|
|
index = (addr >> 4) & 0xff;
|
|
switch(index) {
|
|
case 0x02: /* id */
|
|
val = s->id << 24;
|
|
break;
|
|
case 0x03: /* version */
|
|
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
|
|
break;
|
|
case 0x08:
|
|
val = s->tpr;
|
|
break;
|
|
case 0x09:
|
|
val = apic_get_arb_pri(s);
|
|
break;
|
|
case 0x0a:
|
|
/* ppr */
|
|
val = apic_get_ppr(s);
|
|
break;
|
|
case 0x0b:
|
|
val = 0;
|
|
break;
|
|
case 0x0d:
|
|
val = s->log_dest << 24;
|
|
break;
|
|
case 0x0e:
|
|
val = s->dest_mode << 28;
|
|
break;
|
|
case 0x0f:
|
|
val = s->spurious_vec;
|
|
break;
|
|
case 0x10 ... 0x17:
|
|
val = s->isr[index & 7];
|
|
break;
|
|
case 0x18 ... 0x1f:
|
|
val = s->tmr[index & 7];
|
|
break;
|
|
case 0x20 ... 0x27:
|
|
val = s->irr[index & 7];
|
|
break;
|
|
case 0x28:
|
|
val = s->esr;
|
|
break;
|
|
case 0x30:
|
|
case 0x31:
|
|
val = s->icr[index & 1];
|
|
break;
|
|
case 0x32 ... 0x37:
|
|
val = s->lvt[index - 0x32];
|
|
break;
|
|
case 0x38:
|
|
val = s->initial_count;
|
|
break;
|
|
case 0x39:
|
|
val = apic_get_current_count(s);
|
|
break;
|
|
case 0x3e:
|
|
val = s->divide_conf;
|
|
break;
|
|
default:
|
|
s->esr |= ESR_ILLEGAL_ADDRESS;
|
|
val = 0;
|
|
break;
|
|
}
|
|
#ifdef DEBUG_APIC
|
|
printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
static void apic_send_msi(target_phys_addr_t addr, uint32 data)
|
|
{
|
|
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
|
|
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
|
|
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
|
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
|
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
|
/* XXX: Ignore redirection hint. */
|
|
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
|
}
|
|
|
|
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
CPUState *env;
|
|
APICState *s;
|
|
int index = (addr >> 4) & 0xff;
|
|
if (addr > 0xfff || !index) {
|
|
/* MSI and MMIO APIC are at the same memory location,
|
|
* but actually not on the global bus: MSI is on PCI bus
|
|
* APIC is connected directly to the CPU.
|
|
* Mapping them on the global bus happens to work because
|
|
* MSI registers are reserved in APIC MMIO and vice versa. */
|
|
apic_send_msi(addr, val);
|
|
return;
|
|
}
|
|
|
|
env = cpu_single_env;
|
|
if (!env)
|
|
return;
|
|
s = env->apic_state;
|
|
|
|
#ifdef DEBUG_APIC
|
|
printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
|
#endif
|
|
|
|
switch(index) {
|
|
case 0x02:
|
|
s->id = (val >> 24);
|
|
break;
|
|
case 0x03:
|
|
break;
|
|
case 0x08:
|
|
s->tpr = val;
|
|
apic_update_irq(s);
|
|
break;
|
|
case 0x09:
|
|
case 0x0a:
|
|
break;
|
|
case 0x0b: /* EOI */
|
|
apic_eoi(s);
|
|
break;
|
|
case 0x0d:
|
|
s->log_dest = val >> 24;
|
|
break;
|
|
case 0x0e:
|
|
s->dest_mode = val >> 28;
|
|
break;
|
|
case 0x0f:
|
|
s->spurious_vec = val & 0x1ff;
|
|
apic_update_irq(s);
|
|
break;
|
|
case 0x10 ... 0x17:
|
|
case 0x18 ... 0x1f:
|
|
case 0x20 ... 0x27:
|
|
case 0x28:
|
|
break;
|
|
case 0x30:
|
|
s->icr[0] = val;
|
|
apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
|
|
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
|
|
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
|
|
break;
|
|
case 0x31:
|
|
s->icr[1] = val;
|
|
break;
|
|
case 0x32 ... 0x37:
|
|
{
|
|
int n = index - 0x32;
|
|
s->lvt[n] = val;
|
|
if (n == APIC_LVT_TIMER)
|
|
apic_timer_update(s, qemu_get_clock(vm_clock));
|
|
}
|
|
break;
|
|
case 0x38:
|
|
s->initial_count = val;
|
|
s->initial_count_load_time = qemu_get_clock(vm_clock);
|
|
apic_timer_update(s, s->initial_count_load_time);
|
|
break;
|
|
case 0x39:
|
|
break;
|
|
case 0x3e:
|
|
{
|
|
int v;
|
|
s->divide_conf = val & 0xb;
|
|
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
|
|
s->count_shift = (v + 1) & 7;
|
|
}
|
|
break;
|
|
default:
|
|
s->esr |= ESR_ILLEGAL_ADDRESS;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* This function is only used for old state version 1 and 2 */
|
|
static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
APICState *s = opaque;
|
|
int i;
|
|
|
|
if (version_id > 2)
|
|
return -EINVAL;
|
|
|
|
/* XXX: what if the base changes? (registered memory regions) */
|
|
qemu_get_be32s(f, &s->apicbase);
|
|
qemu_get_8s(f, &s->id);
|
|
qemu_get_8s(f, &s->arb_id);
|
|
qemu_get_8s(f, &s->tpr);
|
|
qemu_get_be32s(f, &s->spurious_vec);
|
|
qemu_get_8s(f, &s->log_dest);
|
|
qemu_get_8s(f, &s->dest_mode);
|
|
for (i = 0; i < 8; i++) {
|
|
qemu_get_be32s(f, &s->isr[i]);
|
|
qemu_get_be32s(f, &s->tmr[i]);
|
|
qemu_get_be32s(f, &s->irr[i]);
|
|
}
|
|
for (i = 0; i < APIC_LVT_NB; i++) {
|
|
qemu_get_be32s(f, &s->lvt[i]);
|
|
}
|
|
qemu_get_be32s(f, &s->esr);
|
|
qemu_get_be32s(f, &s->icr[0]);
|
|
qemu_get_be32s(f, &s->icr[1]);
|
|
qemu_get_be32s(f, &s->divide_conf);
|
|
s->count_shift=qemu_get_be32(f);
|
|
qemu_get_be32s(f, &s->initial_count);
|
|
s->initial_count_load_time=qemu_get_be64(f);
|
|
s->next_time=qemu_get_be64(f);
|
|
|
|
if (version_id >= 2)
|
|
qemu_get_timer(f, s->timer);
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_apic = {
|
|
.name = "apic",
|
|
.version_id = 3,
|
|
.minimum_version_id = 3,
|
|
.minimum_version_id_old = 1,
|
|
.load_state_old = apic_load_old,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_UINT32(apicbase, APICState),
|
|
VMSTATE_UINT8(id, APICState),
|
|
VMSTATE_UINT8(arb_id, APICState),
|
|
VMSTATE_UINT8(tpr, APICState),
|
|
VMSTATE_UINT32(spurious_vec, APICState),
|
|
VMSTATE_UINT8(log_dest, APICState),
|
|
VMSTATE_UINT8(dest_mode, APICState),
|
|
VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
|
VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
|
VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
|
VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
|
|
VMSTATE_UINT32(esr, APICState),
|
|
VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
|
VMSTATE_UINT32(divide_conf, APICState),
|
|
VMSTATE_INT32(count_shift, APICState),
|
|
VMSTATE_UINT32(initial_count, APICState),
|
|
VMSTATE_INT64(initial_count_load_time, APICState),
|
|
VMSTATE_INT64(next_time, APICState),
|
|
VMSTATE_TIMER(timer, APICState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void apic_reset(void *opaque)
|
|
{
|
|
APICState *s = opaque;
|
|
int bsp;
|
|
|
|
cpu_synchronize_state(s->cpu_env);
|
|
|
|
bsp = cpu_is_bsp(s->cpu_env);
|
|
s->apicbase = 0xfee00000 |
|
|
(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
|
|
|
cpu_reset(s->cpu_env);
|
|
apic_init_reset(s->cpu_env);
|
|
|
|
if (bsp) {
|
|
/*
|
|
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
|
* time typically by BIOS, so PIC interrupt can be delivered to the
|
|
* processor when local APIC is enabled.
|
|
*/
|
|
s->lvt[APIC_LVT_LINT0] = 0x700;
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const apic_mem_read[3] = {
|
|
apic_mem_readb,
|
|
apic_mem_readw,
|
|
apic_mem_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const apic_mem_write[3] = {
|
|
apic_mem_writeb,
|
|
apic_mem_writew,
|
|
apic_mem_writel,
|
|
};
|
|
|
|
int apic_init(CPUState *env)
|
|
{
|
|
APICState *s;
|
|
|
|
if (last_apic_idx >= MAX_APICS)
|
|
return -1;
|
|
s = qemu_mallocz(sizeof(APICState));
|
|
env->apic_state = s;
|
|
s->idx = last_apic_idx++;
|
|
s->id = env->cpuid_apic_id;
|
|
s->cpu_env = env;
|
|
|
|
apic_reset(s);
|
|
msix_supported = 1;
|
|
|
|
/* XXX: mapping more APICs at the same memory location */
|
|
if (apic_io_memory == 0) {
|
|
/* NOTE: the APIC is directly connected to the CPU - it is not
|
|
on the global memory bus. */
|
|
apic_io_memory = cpu_register_io_memory(apic_mem_read,
|
|
apic_mem_write, NULL);
|
|
/* XXX: what if the base changes? */
|
|
cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
|
|
apic_io_memory);
|
|
}
|
|
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
|
|
|
|
vmstate_register(s->idx, &vmstate_apic, s);
|
|
qemu_register_reset(apic_reset, s);
|
|
|
|
local_apics[s->idx] = s;
|
|
return 0;
|
|
}
|