qemu-e2k/target/riscv
Alistair Francis 71b76da33a target/riscv: Ensure mideleg is set correctly on reset
Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor is
enabled. We currently only set them on accesses to mideleg, but they
aren't correctly set on reset. Let's ensure they are always the correct
value.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1617
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-4-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10 18:47:47 +10:00
..
insn_trans target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
kvm target/riscv/kvm: add RVV and Vector CSR regs 2024-01-10 18:47:47 +10:00
tcg target/riscv: add 'parent' in profile description 2024-01-10 18:47:47 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h
cpu_cfg.h target/riscv: implement svade 2024-01-10 18:47:47 +10:00
cpu_helper.c target/riscv: Don't adjust vscause for exceptions 2024-01-10 18:47:47 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target/riscv: add rva22s64 cpu 2024-01-10 18:47:47 +10:00
cpu.c target/riscv: Ensure mideleg is set correctly on reset 2024-01-10 18:47:47 +10:00
cpu.h target/riscv: add 'parent' in profile description 2024-01-10 18:47:47 +10:00
crypto_helper.c
csr.c target/riscv: Assert that the CSR numbers will be correct 2024-01-10 18:47:47 +10:00
debug.c
debug.h
fpu_helper.c
gdbstub.c
helper.h
insn16.decode
insn32.decode target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
instmap.h
internals.h
Kconfig
m128_helper.c
machine.c target/riscv: Constify VMState in machine.c 2023-12-29 11:17:30 +11:00
meson.build
monitor.c
op_helper.c
pmp.c target/riscv: pmp: Ignore writes when RW=01 and MML=0 2024-01-10 18:47:47 +10:00
pmp.h target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 2024-01-10 18:47:46 +10:00
pmu.c
pmu.h
riscv-qmp-cmds.c riscv-qmp-cmds.c: add profile flags in cpu-model-expansion 2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
vcrypto_helper.c
vector_helper.c
vector_internals.c
vector_internals.h
xthead.decode
XVentanaCondOps.decode
zce_helper.c