Peter Maydell 5454006a7c hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU ... Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-5-git-send-email-peter.maydell@linaro.org		2017-01-20 11:15:09 +00:00
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allwinner-a10.h
arm.h	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
aspeed_soc.h	aspeed: add a memory region for SRAM	2016-12-27 14:59:27 +00:00
bcm2835_peripherals.h
bcm2836.h
digic.h
exynos4210.h	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
fdt.h
fsl-imx6.h
fsl-imx25.h
fsl-imx31.h
linux-boot-if.h
omap.h	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
primecell.h
pxa.h	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
raspi_platform.h
sharpsl.h
soc_dma.h
stm32f205_soc.h	STM32F205: Connect the SPI devices	2016-10-04 13:28:07 +01:00
sysbus-fdt.h
virt.h	hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU	2017-01-20 11:15:09 +00:00
xlnx-zynqmp.h