141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
#ifndef E2K_CPU_H
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#define E2K_CPU_H
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#include "qemu/bswap.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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void e2k_tcg_initialize(void);
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#define MMU_USER_IDX 1
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#define CPU_RESOLVING_TYPE TYPE_E2K_CPU
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#define WREGS_SIZE 192
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// size of regular reg in bytes
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#define REG_SIZE (sizeof(target_ulong))
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#define CTPR_BASE_OFF 0
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#define CTPR_BASE_END 47
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#define CTPR_TAG_OFF 54
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#define CTPR_TAG_END 56
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#define CTPR_OPC_OFF 57
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#define CTPR_OPC_END 58
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#define CTPR_IPD_OFF 59
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#define CTPR_IPD_END 60
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#define LSR_LCNT_OFF 0 /* loop counter */
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#define LSR_LCNT_END 31
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#define LSR_LCNT_LEN (LSR_LCNT_END - LSR_LCNT_OFF + 1)
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#define LSR_ECNT_OFF 32 /* epilogue counter */
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#define LSR_ECNT_END 36
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#define LSR_ECNT_LEN (LSR_ECNT_END - LSR_ECNT_OFF + 1)
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#define LSR_VLC_OFF 37 /* loop count valid bit */
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#define LSR_OVER_OFF 38 /* loop count overflow */
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#define LSR_LDMC_OFF 39 /* loads manual control */
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#define LSR_LDOVL_OFF 40 /* load overlap */
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#define LSR_LDOVL_END 47
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#define LSR_LDOVL_SIZE (LSR_LDOVL_END - LSR_LDOVL_OFF + 1)
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#define LSR_PCNT_OFF 48 /* prologue counter */
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#define LSR_PCNT_END 52
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#define LSR_PCNT_LEN (LSR_PCNT_END - LSR_PCNT_OFF + 1)
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#define LSR_STRMD_OFF 53 /* store remainder counter */
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#define LSR_STRMD_END 59
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#define LSR_STRMD_LEN (LSR_STRMD_END - LSR_STRMD_OFF + 1)
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#define LSR_SEMC_OFF /* side effects manual control */
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typedef enum {
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E2K_EXCP_UNIMPL = 0x01,
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E2K_EXCP_SYSCALL = 0x02,
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} Exception;
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struct e2k_def_t {
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const char *name;
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uint32_t isa_version;
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};
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typedef struct CPUArchState {
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/* register file */
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target_ulong gregs[32]; // global regs
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target_ulong wregs[WREGS_SIZE]; // window regs
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target_ulong *win_ptr;
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uint64_t pregs;
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uint32_t wbs; // window regs offset
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uint32_t wsz; // window regs size
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uint32_t nfx; // TODO
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uint32_t dbl; // TODO
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/* TODO: move them to %br? */
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uint32_t rbs; // based regs offset
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uint32_t rsz; // based regs size
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uint32_t rcur; // based regs current offset
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uint64_t psz; // pred regs window size
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uint64_t pcur; // pred regs current offset
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uint64_t lsr; /* loop status register */
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uint32_t syscall_wbs;
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uint64_t usd_lo;
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uint64_t usd_hi;
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/* control registers */
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target_ulong ctprs[3]; // Control Transfer Preparation Register (CTPR)
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/* special registers */
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target_ulong ip; /* instruction address, next instruction address */
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uint32_t pfpfr; // Packed Floating Point Flag Register (PFPFR)
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uint32_t fpcr; // Floating point control register (FPCR)
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uint32_t fpsr; // Floating point state register (FPSR)
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int interrupt_index;
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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uint32_t version;
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struct e2k_def_t def;
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} CPUE2KState;
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/**
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* E2KCPU:
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* @env: #CPUE2KState
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*
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* An Elbrus CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUE2KState env;
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};
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static inline void cpu_get_tb_cpu_state(CPUE2KState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *pflags)
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{
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*pc = env->ip;
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*cs_base = 0;
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*pflags = MMU_USER_IDX;
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}
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static inline int cpu_mmu_index(CPUE2KState *env, bool ifetch)
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{
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#ifdef CONFIG_USER_ONLY
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return MMU_USER_IDX;
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#else
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#error softmmu is not supported on E2K
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#endif
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}
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int e2k_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
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#define cpu_signal_handler e2k_cpu_signal_handler
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#include "exec/cpu-all.h"
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#endif
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