3cd27b58dd
VMStateDescription.fields should be end with VMSTATE_END_OF_LIST().
However, microbit_i2c_vmstate doesn't follow it. Let's change it.
Fixes: 9d68bf564e ("arm: Stub out NRF51 TWI magnetometer/accelerometer detection")
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201019093401.2993833-1-liangpeng10@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
131 lines
3.6 KiB
C
131 lines
3.6 KiB
C
/*
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* Microbit stub for Nordic Semiconductor nRF51 SoC Two-Wire Interface
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* http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
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*
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* This is a microbit-specific stub for the TWI controller on the nRF51 SoC.
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* We don't emulate I2C devices but the firmware probes the
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* accelerometer/magnetometer on startup and panics if they are not found.
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* Therefore we stub out the probing.
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*
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* In the future this file could evolve into a full nRF51 TWI controller
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* device.
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*
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* Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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* Copyright 2019 Red Hat, Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/i2c/microbit_i2c.h"
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#include "migration/vmstate.h"
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static const uint32_t twi_read_sequence[] = {0x5A, 0x5A, 0x40};
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static uint64_t microbit_i2c_read(void *opaque, hwaddr addr, unsigned int size)
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{
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MicrobitI2CState *s = opaque;
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uint64_t data = 0x00;
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switch (addr) {
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case NRF51_TWI_EVENT_STOPPED:
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data = 0x01;
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break;
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case NRF51_TWI_EVENT_RXDREADY:
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data = 0x01;
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break;
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case NRF51_TWI_EVENT_TXDSENT:
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data = 0x01;
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break;
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case NRF51_TWI_REG_RXD:
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data = twi_read_sequence[s->read_idx];
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if (s->read_idx < G_N_ELEMENTS(twi_read_sequence)) {
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s->read_idx++;
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}
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break;
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default:
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data = s->regs[addr / sizeof(s->regs[0])];
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break;
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}
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u] = %" PRIx32 "\n",
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__func__, addr, size, (uint32_t)data);
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return data;
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}
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static void microbit_i2c_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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MicrobitI2CState *s = opaque;
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
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__func__, addr, data, size);
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s->regs[addr / sizeof(s->regs[0])] = data;
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}
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static const MemoryRegionOps microbit_i2c_ops = {
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.read = microbit_i2c_read,
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.write = microbit_i2c_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static const VMStateDescription microbit_i2c_vmstate = {
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.name = TYPE_MICROBIT_I2C,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, MicrobitI2CState, MICROBIT_I2C_NREGS),
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VMSTATE_UINT32(read_idx, MicrobitI2CState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void microbit_i2c_reset(DeviceState *dev)
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{
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MicrobitI2CState *s = MICROBIT_I2C(dev);
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memset(s->regs, 0, sizeof(s->regs));
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s->read_idx = 0;
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}
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static void microbit_i2c_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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MicrobitI2CState *s = MICROBIT_I2C(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), µbit_i2c_ops, s,
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"microbit.twi", NRF51_PERIPHERAL_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void microbit_i2c_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = µbit_i2c_vmstate;
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dc->reset = microbit_i2c_reset;
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dc->realize = microbit_i2c_realize;
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dc->desc = "Microbit I2C controller";
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}
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static const TypeInfo microbit_i2c_info = {
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.name = TYPE_MICROBIT_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MicrobitI2CState),
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.class_init = microbit_i2c_class_init,
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};
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static void microbit_i2c_register_types(void)
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{
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type_register_static(µbit_i2c_info);
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}
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type_init(microbit_i2c_register_types)
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