f436ecc315
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/*
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* SiFive PLIC (Platform Level Interrupt Controller) interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This provides a RISC-V PLIC device
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_PLIC_H
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#define HW_SIFIVE_PLIC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
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typedef struct SiFivePLICState SiFivePLICState;
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DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC,
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TYPE_SIFIVE_PLIC)
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typedef enum PLICMode {
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PLICMode_U,
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PLICMode_S,
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PLICMode_H,
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PLICMode_M
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} PLICMode;
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typedef struct PLICAddr {
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uint32_t addrid;
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uint32_t hartid;
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PLICMode mode;
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} PLICAddr;
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struct SiFivePLICState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t num_addrs;
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uint32_t num_harts;
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uint32_t bitfield_words;
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uint32_t num_enables;
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PLICAddr *addr_config;
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uint32_t *source_priority;
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uint32_t *target_priority;
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uint32_t *pending;
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uint32_t *claimed;
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uint32_t *enable;
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/* config */
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char *hart_config;
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uint32_t hartid_base;
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uint32_t num_sources;
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uint32_t num_priorities;
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uint32_t priority_base;
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uint32_t pending_base;
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uint32_t enable_base;
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uint32_t enable_stride;
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uint32_t context_base;
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uint32_t context_stride;
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uint32_t aperture_size;
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qemu_irq *m_external_irqs;
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qemu_irq *s_external_irqs;
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};
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DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
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uint32_t num_harts,
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uint32_t hartid_base, uint32_t num_sources,
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uint32_t num_priorities, uint32_t priority_base,
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uint32_t pending_base, uint32_t enable_base,
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uint32_t enable_stride, uint32_t context_base,
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uint32_t context_stride, uint32_t aperture_size);
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#endif
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