726 lines
22 KiB
C
726 lines
22 KiB
C
/*
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* ARM Generic/Distributed Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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/* This file contains implementation code for the RealView EB interrupt
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* controller, MPCore distributed interrupt controller and ARMv7-M
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* Nested Vectored Interrupt Controller.
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* It is compiled in two ways:
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* (1) as a standalone file to produce a sysbus device which is a GIC
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* that can be used on the realview board and as one of the builtin
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* private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
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* (2) by being directly #included into armv7m_nvic.c to produce the
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* armv7m_nvic device.
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*/
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#include "hw/sysbus.h"
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#include "gic_internal.h"
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#include "qom/cpu.h"
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//#define DEBUG_GIC
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#ifdef DEBUG_GIC
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif
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static const uint8_t gic_id[] = {
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0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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#define NUM_CPU(s) ((s)->num_cpu)
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static inline int gic_get_current_cpu(GICState *s)
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{
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if (s->num_cpu > 1) {
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return current_cpu->cpu_index;
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}
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return 0;
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}
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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void gic_update(GICState *s)
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{
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int best_irq;
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int best_prio;
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int irq;
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int level;
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int cpu;
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int cm;
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for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
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cm = 1 << cpu;
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s->current_pending[cpu] = 1023;
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if (!s->enabled || !s->cpu_enabled[cpu]) {
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qemu_irq_lower(s->parent_irq[cpu]);
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return;
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}
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best_prio = 0x100;
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best_irq = 1023;
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for (irq = 0; irq < s->num_irq; irq++) {
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if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
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if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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best_prio = GIC_GET_PRIORITY(irq, cpu);
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best_irq = irq;
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}
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}
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}
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level = 0;
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if (best_prio < s->priority_mask[cpu]) {
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s->current_pending[cpu] = best_irq;
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if (best_prio < s->running_priority[cpu]) {
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DPRINTF("Raised pending IRQ %d (cpu %d)\n", best_irq, cpu);
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level = 1;
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}
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}
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qemu_set_irq(s->parent_irq[cpu], level);
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}
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}
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void gic_set_pending_private(GICState *s, int cpu, int irq)
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{
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int cm = 1 << cpu;
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if (GIC_TEST_PENDING(irq, cm))
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return;
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DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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GIC_SET_PENDING(irq, cm);
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gic_update(s);
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}
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/* Process a change in an external IRQ input. */
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static void gic_set_irq(void *opaque, int irq, int level)
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{
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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GICState *s = (GICState *)opaque;
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int cm, target;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* The first external input line is internal interrupt 32. */
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cm = ALL_CPU_MASK;
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irq += GIC_INTERNAL;
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target = GIC_TARGET(irq);
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} else {
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int cpu;
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irq -= (s->num_irq - GIC_INTERNAL);
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cpu = irq / GIC_INTERNAL;
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irq %= GIC_INTERNAL;
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cm = 1 << cpu;
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target = cm;
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}
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if (level == GIC_TEST_LEVEL(irq, cm)) {
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return;
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}
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if (level) {
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GIC_SET_LEVEL(irq, cm);
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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DPRINTF("Set %d pending mask %x\n", irq, target);
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GIC_SET_PENDING(irq, target);
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}
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} else {
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GIC_CLEAR_LEVEL(irq, cm);
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}
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gic_update(s);
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}
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static void gic_set_running_irq(GICState *s, int cpu, int irq)
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{
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s->running_irq[cpu] = irq;
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if (irq == 1023) {
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s->running_priority[cpu] = 0x100;
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} else {
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s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
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}
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gic_update(s);
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}
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uint32_t gic_acknowledge_irq(GICState *s, int cpu)
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{
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int new_irq;
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int cm = 1 << cpu;
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new_irq = s->current_pending[cpu];
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if (new_irq == 1023
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|| GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
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DPRINTF("ACK no pending IRQ\n");
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return 1023;
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}
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s->last_active[new_irq][cpu] = s->running_irq[cpu];
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/* Clear pending flags for both level and edge triggered interrupts.
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Level triggered IRQs will be reasserted once they become inactive. */
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GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
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gic_set_running_irq(s, cpu, new_irq);
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DPRINTF("ACK %d\n", new_irq);
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return new_irq;
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}
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void gic_complete_irq(GICState *s, int cpu, int irq)
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{
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int update = 0;
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int cm = 1 << cpu;
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DPRINTF("EOI %d\n", irq);
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if (irq >= s->num_irq) {
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/* This handles two cases:
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* 1. If software writes the ID of a spurious interrupt [ie 1023]
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* to the GICC_EOIR, the GIC ignores that write.
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* 2. If software writes the number of a non-existent interrupt
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* this must be a subcase of "value written does not match the last
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* valid interrupt value read from the Interrupt Acknowledge
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* register" and so this is UNPREDICTABLE. We choose to ignore it.
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*/
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return;
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}
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if (s->running_irq[cpu] == 1023)
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return; /* No active IRQ. */
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/* Mark level triggered interrupts as pending if they are still
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raised. */
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if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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DPRINTF("Set %d pending mask %x\n", irq, cm);
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GIC_SET_PENDING(irq, cm);
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update = 1;
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}
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if (irq != s->running_irq[cpu]) {
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/* Complete an IRQ that is not currently running. */
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int tmp = s->running_irq[cpu];
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while (s->last_active[tmp][cpu] != 1023) {
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if (s->last_active[tmp][cpu] == irq) {
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s->last_active[tmp][cpu] = s->last_active[irq][cpu];
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break;
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}
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tmp = s->last_active[tmp][cpu];
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}
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if (update) {
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gic_update(s);
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}
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} else {
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/* Complete the current running IRQ. */
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gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
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}
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}
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static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
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{
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GICState *s = (GICState *)opaque;
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uint32_t res;
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int irq;
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int i;
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int cpu;
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int cm;
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int mask;
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cpu = gic_get_current_cpu(s);
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cm = 1 << cpu;
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if (offset < 0x100) {
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if (offset == 0)
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return s->enabled;
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if (offset == 4)
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return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
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if (offset < 0x08)
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return 0;
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if (offset >= 0x80) {
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/* Interrupt Security , RAZ/WI */
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return 0;
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}
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goto bad_reg;
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} else if (offset < 0x200) {
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/* Interrupt Set/Clear Enable. */
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if (offset < 0x180)
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irq = (offset - 0x100) * 8;
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else
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irq = (offset - 0x180) * 8;
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irq += GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_ENABLED(irq + i, cm)) {
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res |= (1 << i);
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}
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}
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} else if (offset < 0x300) {
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/* Interrupt Set/Clear Pending. */
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if (offset < 0x280)
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irq = (offset - 0x200) * 8;
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else
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irq = (offset - 0x280) * 8;
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irq += GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_PENDING(irq + i, mask)) {
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res |= (1 << i);
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}
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}
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} else if (offset < 0x400) {
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/* Interrupt Active. */
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irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
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for (i = 0; i < 8; i++) {
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if (GIC_TEST_ACTIVE(irq + i, mask)) {
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res |= (1 << i);
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}
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}
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = (offset - 0x400) + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = GIC_GET_PRIORITY(irq, cpu);
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} else if (offset < 0xc00) {
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/* Interrupt CPU Target. */
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if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
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/* For uniprocessor GICs these RAZ/WI */
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res = 0;
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} else {
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irq = (offset - 0x800) + GIC_BASE_IRQ;
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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if (irq >= 29 && irq <= 31) {
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res = cm;
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} else {
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res = GIC_TARGET(irq);
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}
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}
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 4; i++) {
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if (GIC_TEST_MODEL(irq + i))
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res |= (1 << (i * 2));
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if (GIC_TEST_TRIGGER(irq + i))
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res |= (2 << (i * 2));
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}
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} else if (offset < 0xfe0) {
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goto bad_reg;
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} else /* offset >= 0xfe0 */ {
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if (offset & 3) {
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res = 0;
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} else {
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res = gic_id[(offset - 0xfe0) >> 2];
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}
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}
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return res;
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bad_reg:
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qemu_log_mask(LOG_GUEST_ERROR,
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"gic_dist_readb: Bad offset %x\n", (int)offset);
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return 0;
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}
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static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
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{
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uint32_t val;
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val = gic_dist_readb(opaque, offset);
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val |= gic_dist_readb(opaque, offset + 1) << 8;
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return val;
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}
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static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
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{
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uint32_t val;
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val = gic_dist_readw(opaque, offset);
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val |= gic_dist_readw(opaque, offset + 2) << 16;
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return val;
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}
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static void gic_dist_writeb(void *opaque, hwaddr offset,
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uint32_t value)
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{
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GICState *s = (GICState *)opaque;
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int irq;
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int i;
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int cpu;
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cpu = gic_get_current_cpu(s);
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if (offset < 0x100) {
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if (offset == 0) {
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s->enabled = (value & 1);
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DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
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} else if (offset < 4) {
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/* ignored. */
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} else if (offset >= 0x80) {
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/* Interrupt Security Registers, RAZ/WI */
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} else {
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goto bad_reg;
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}
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} else if (offset < 0x180) {
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/* Interrupt Set Enable. */
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irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < 16)
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value = 0xff;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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int mask =
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(irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (!GIC_TEST_ENABLED(irq + i, cm)) {
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DPRINTF("Enabled IRQ %d\n", irq + i);
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}
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GIC_SET_ENABLED(irq + i, cm);
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/* If a raised level triggered IRQ enabled then mark
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is as pending. */
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if (GIC_TEST_LEVEL(irq + i, mask)
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&& !GIC_TEST_TRIGGER(irq + i)) {
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DPRINTF("Set %d pending mask %x\n", irq + i, mask);
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GIC_SET_PENDING(irq + i, mask);
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}
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}
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}
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} else if (offset < 0x200) {
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/* Interrupt Clear Enable. */
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irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < 16)
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value = 0;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (GIC_TEST_ENABLED(irq + i, cm)) {
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DPRINTF("Disabled IRQ %d\n", irq + i);
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}
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GIC_CLEAR_ENABLED(irq + i, cm);
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}
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}
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} else if (offset < 0x280) {
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/* Interrupt Set Pending. */
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irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < 16)
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irq = 0;
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for (i = 0; i < 8; i++) {
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if (value & (1 << i)) {
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GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i));
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}
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}
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} else if (offset < 0x300) {
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/* Interrupt Clear Pending. */
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irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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for (i = 0; i < 8; i++) {
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/* ??? This currently clears the pending bit for all CPUs, even
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for per-CPU interrupts. It's unclear whether this is the
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corect behavior. */
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if (value & (1 << i)) {
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GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
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}
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}
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} else if (offset < 0x400) {
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/* Interrupt Active. */
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goto bad_reg;
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = (offset - 0x400) + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_INTERNAL) {
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s->priority1[irq][cpu] = value;
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} else {
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s->priority2[irq - GIC_INTERNAL] = value;
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}
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} else if (offset < 0xc00) {
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/* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
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* annoying exception of the 11MPCore's GIC.
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*/
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if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
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irq = (offset - 0x800) + GIC_BASE_IRQ;
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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if (irq < 29) {
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value = 0;
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} else if (irq < GIC_INTERNAL) {
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value = ALL_CPU_MASK;
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}
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s->irq_target[irq] = value & ALL_CPU_MASK;
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}
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_INTERNAL)
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value |= 0xaa;
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for (i = 0; i < 4; i++) {
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if (value & (1 << (i * 2))) {
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GIC_SET_MODEL(irq + i);
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} else {
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GIC_CLEAR_MODEL(irq + i);
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}
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if (value & (2 << (i * 2))) {
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GIC_SET_TRIGGER(irq + i);
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} else {
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GIC_CLEAR_TRIGGER(irq + i);
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}
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}
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} else {
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/* 0xf00 is only handled for 32-bit writes. */
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goto bad_reg;
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}
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gic_update(s);
|
|
return;
|
|
bad_reg:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"gic_dist_writeb: Bad offset %x\n", (int)offset);
|
|
}
|
|
|
|
static void gic_dist_writew(void *opaque, hwaddr offset,
|
|
uint32_t value)
|
|
{
|
|
gic_dist_writeb(opaque, offset, value & 0xff);
|
|
gic_dist_writeb(opaque, offset + 1, value >> 8);
|
|
}
|
|
|
|
static void gic_dist_writel(void *opaque, hwaddr offset,
|
|
uint32_t value)
|
|
{
|
|
GICState *s = (GICState *)opaque;
|
|
if (offset == 0xf00) {
|
|
int cpu;
|
|
int irq;
|
|
int mask;
|
|
|
|
cpu = gic_get_current_cpu(s);
|
|
irq = value & 0x3ff;
|
|
switch ((value >> 24) & 3) {
|
|
case 0:
|
|
mask = (value >> 16) & ALL_CPU_MASK;
|
|
break;
|
|
case 1:
|
|
mask = ALL_CPU_MASK ^ (1 << cpu);
|
|
break;
|
|
case 2:
|
|
mask = 1 << cpu;
|
|
break;
|
|
default:
|
|
DPRINTF("Bad Soft Int target filter\n");
|
|
mask = ALL_CPU_MASK;
|
|
break;
|
|
}
|
|
GIC_SET_PENDING(irq, mask);
|
|
gic_update(s);
|
|
return;
|
|
}
|
|
gic_dist_writew(opaque, offset, value & 0xffff);
|
|
gic_dist_writew(opaque, offset + 2, value >> 16);
|
|
}
|
|
|
|
static const MemoryRegionOps gic_dist_ops = {
|
|
.old_mmio = {
|
|
.read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
|
|
.write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
|
|
},
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static uint32_t gic_cpu_read(GICState *s, int cpu, int offset)
|
|
{
|
|
switch (offset) {
|
|
case 0x00: /* Control */
|
|
return s->cpu_enabled[cpu];
|
|
case 0x04: /* Priority mask */
|
|
return s->priority_mask[cpu];
|
|
case 0x08: /* Binary Point */
|
|
/* ??? Not implemented. */
|
|
return 0;
|
|
case 0x0c: /* Acknowledge */
|
|
return gic_acknowledge_irq(s, cpu);
|
|
case 0x14: /* Running Priority */
|
|
return s->running_priority[cpu];
|
|
case 0x18: /* Highest Pending Interrupt */
|
|
return s->current_pending[cpu];
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"gic_cpu_read: Bad offset %x\n", (int)offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
|
|
{
|
|
switch (offset) {
|
|
case 0x00: /* Control */
|
|
s->cpu_enabled[cpu] = (value & 1);
|
|
DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis");
|
|
break;
|
|
case 0x04: /* Priority mask */
|
|
s->priority_mask[cpu] = (value & 0xff);
|
|
break;
|
|
case 0x08: /* Binary Point */
|
|
/* ??? Not implemented. */
|
|
break;
|
|
case 0x10: /* End Of Interrupt */
|
|
return gic_complete_irq(s, cpu, value & 0x3ff);
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"gic_cpu_write: Bad offset %x\n", (int)offset);
|
|
return;
|
|
}
|
|
gic_update(s);
|
|
}
|
|
|
|
/* Wrappers to read/write the GIC CPU interface for the current CPU */
|
|
static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
GICState *s = (GICState *)opaque;
|
|
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
|
|
}
|
|
|
|
static void gic_thiscpu_write(void *opaque, hwaddr addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
GICState *s = (GICState *)opaque;
|
|
gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
|
|
}
|
|
|
|
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
|
|
* These just decode the opaque pointer into GICState* + cpu id.
|
|
*/
|
|
static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
GICState **backref = (GICState **)opaque;
|
|
GICState *s = *backref;
|
|
int id = (backref - s->backref);
|
|
return gic_cpu_read(s, id, addr);
|
|
}
|
|
|
|
static void gic_do_cpu_write(void *opaque, hwaddr addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
GICState **backref = (GICState **)opaque;
|
|
GICState *s = *backref;
|
|
int id = (backref - s->backref);
|
|
gic_cpu_write(s, id, addr, value);
|
|
}
|
|
|
|
static const MemoryRegionOps gic_thiscpu_ops = {
|
|
.read = gic_thiscpu_read,
|
|
.write = gic_thiscpu_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static const MemoryRegionOps gic_cpu_ops = {
|
|
.read = gic_do_cpu_read,
|
|
.write = gic_do_cpu_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
void gic_init_irqs_and_distributor(GICState *s, int num_irq)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
|
|
int i;
|
|
|
|
i = s->num_irq - GIC_INTERNAL;
|
|
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
|
|
* GPIO array layout is thus:
|
|
* [0..N-1] SPIs
|
|
* [N..N+31] PPIs for CPU 0
|
|
* [N+32..N+63] PPIs for CPU 1
|
|
* ...
|
|
*/
|
|
if (s->revision != REV_NVIC) {
|
|
i += (GIC_INTERNAL * s->num_cpu);
|
|
}
|
|
qdev_init_gpio_in(DEVICE(s), gic_set_irq, i);
|
|
for (i = 0; i < NUM_CPU(s); i++) {
|
|
sysbus_init_irq(sbd, &s->parent_irq[i]);
|
|
}
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s,
|
|
"gic_dist", 0x1000);
|
|
}
|
|
|
|
static void arm_gic_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
/* Device instance realize function for the GIC sysbus device */
|
|
int i;
|
|
GICState *s = ARM_GIC(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
|
|
|
|
agc->parent_realize(dev, errp);
|
|
if (error_is_set(errp)) {
|
|
return;
|
|
}
|
|
|
|
gic_init_irqs_and_distributor(s, s->num_irq);
|
|
|
|
/* Memory regions for the CPU interfaces (NVIC doesn't have these):
|
|
* a region for "CPU interface for this core", then a region for
|
|
* "CPU interface for core 0", "for core 1", ...
|
|
* NB that the memory region size of 0x100 applies for the 11MPCore
|
|
* and also cores following the GIC v1 spec (ie A9).
|
|
* GIC v2 defines a larger memory region (0x1000) so this will need
|
|
* to be extended when we implement A15.
|
|
*/
|
|
memory_region_init_io(&s->cpuiomem[0], OBJECT(s), &gic_thiscpu_ops, s,
|
|
"gic_cpu", 0x100);
|
|
for (i = 0; i < NUM_CPU(s); i++) {
|
|
s->backref[i] = s;
|
|
memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
|
|
&s->backref[i], "gic_cpu", 0x100);
|
|
}
|
|
/* Distributor */
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
/* cpu interfaces (one for "current cpu" plus one per cpu) */
|
|
for (i = 0; i <= NUM_CPU(s); i++) {
|
|
sysbus_init_mmio(sbd, &s->cpuiomem[i]);
|
|
}
|
|
}
|
|
|
|
static void arm_gic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ARMGICClass *agc = ARM_GIC_CLASS(klass);
|
|
|
|
dc->no_user = 1;
|
|
agc->parent_realize = dc->realize;
|
|
dc->realize = arm_gic_realize;
|
|
}
|
|
|
|
static const TypeInfo arm_gic_info = {
|
|
.name = TYPE_ARM_GIC,
|
|
.parent = TYPE_ARM_GIC_COMMON,
|
|
.instance_size = sizeof(GICState),
|
|
.class_init = arm_gic_class_init,
|
|
.class_size = sizeof(ARMGICClass),
|
|
};
|
|
|
|
static void arm_gic_register_types(void)
|
|
{
|
|
type_register_static(&arm_gic_info);
|
|
}
|
|
|
|
type_init(arm_gic_register_types)
|