560 lines
18 KiB
C
560 lines
18 KiB
C
/*
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* ARM Nested Vectored Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*
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* The ARMv7M System controller is fairly tightly tied in with the
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* NVIC. Much of that is also implemented here.
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*/
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "hw/arm/arm.h"
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#include "exec/address-spaces.h"
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#include "gic_internal.h"
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typedef struct {
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GICState gic;
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struct {
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uint32_t control;
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uint32_t reload;
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int64_t tick;
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QEMUTimer *timer;
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} systick;
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MemoryRegion sysregmem;
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MemoryRegion gic_iomem_alias;
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MemoryRegion container;
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uint32_t num_irq;
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} nvic_state;
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#define TYPE_NVIC "armv7m_nvic"
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/**
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* NVICClass:
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* @parent_reset: the parent class' reset handler.
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*
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* A model of the v7M NVIC and System Controller
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*/
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typedef struct NVICClass {
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/*< private >*/
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ARMGICClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(DeviceState *dev);
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} NVICClass;
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#define NVIC_CLASS(klass) \
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OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
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#define NVIC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
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#define NVIC(obj) \
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OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
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static const uint8_t nvic_id[] = {
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0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
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};
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/* qemu timers run at 1GHz. We want something closer to 1MHz. */
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#define SYSTICK_SCALE 1000ULL
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#define SYSTICK_ENABLE (1 << 0)
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#define SYSTICK_TICKINT (1 << 1)
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#define SYSTICK_CLKSOURCE (1 << 2)
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#define SYSTICK_COUNTFLAG (1 << 16)
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int system_clock_scale;
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/* Conversion factor from qemu timer to SysTick frequencies. */
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static inline int64_t systick_scale(nvic_state *s)
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{
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if (s->systick.control & SYSTICK_CLKSOURCE)
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return system_clock_scale;
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else
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return 1000;
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}
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static void systick_reload(nvic_state *s, int reset)
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{
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if (reset)
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s->systick.tick = qemu_get_clock_ns(vm_clock);
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s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
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qemu_mod_timer(s->systick.timer, s->systick.tick);
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}
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static void systick_timer_tick(void * opaque)
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{
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nvic_state *s = (nvic_state *)opaque;
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s->systick.control |= SYSTICK_COUNTFLAG;
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if (s->systick.control & SYSTICK_TICKINT) {
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/* Trigger the interrupt. */
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
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}
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if (s->systick.reload == 0) {
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s->systick.control &= ~SYSTICK_ENABLE;
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} else {
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systick_reload(s, 0);
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}
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}
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static void systick_reset(nvic_state *s)
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{
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s->systick.control = 0;
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s->systick.reload = 0;
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s->systick.tick = 0;
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qemu_del_timer(s->systick.timer);
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}
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/* The external routines use the hardware vector numbering, ie. the first
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IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
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void armv7m_nvic_set_pending(void *opaque, int irq)
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{
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nvic_state *s = (nvic_state *)opaque;
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if (irq >= 16)
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irq += 16;
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gic_set_pending_private(&s->gic, 0, irq);
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}
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/* Make pending IRQ active. */
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int armv7m_nvic_acknowledge_irq(void *opaque)
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{
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nvic_state *s = (nvic_state *)opaque;
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uint32_t irq;
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irq = gic_acknowledge_irq(&s->gic, 0);
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if (irq == 1023)
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hw_error("Interrupt but no vector\n");
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if (irq >= 32)
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irq -= 16;
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return irq;
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}
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void armv7m_nvic_complete_irq(void *opaque, int irq)
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{
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nvic_state *s = (nvic_state *)opaque;
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if (irq >= 16)
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irq += 16;
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gic_complete_irq(&s->gic, 0, irq);
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}
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static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
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{
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ARMCPU *cpu;
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uint32_t val;
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int irq;
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switch (offset) {
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case 4: /* Interrupt Control Type. */
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return (s->num_irq / 32) - 1;
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case 0x10: /* SysTick Control and Status. */
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val = s->systick.control;
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s->systick.control &= ~SYSTICK_COUNTFLAG;
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return val;
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case 0x14: /* SysTick Reload Value. */
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return s->systick.reload;
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case 0x18: /* SysTick Current Value. */
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{
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int64_t t;
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if ((s->systick.control & SYSTICK_ENABLE) == 0)
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return 0;
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t = qemu_get_clock_ns(vm_clock);
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if (t >= s->systick.tick)
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return 0;
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val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
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/* The interrupt in triggered when the timer reaches zero.
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However the counter is not reloaded until the next clock
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tick. This is a hack to return zero during the first tick. */
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if (val > s->systick.reload)
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val = 0;
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return val;
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}
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case 0x1c: /* SysTick Calibration Value. */
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return 10000;
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case 0xd00: /* CPUID Base. */
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cpu = ARM_CPU(current_cpu);
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return cpu->env.cp15.c0_cpuid;
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case 0xd04: /* Interrupt Control State. */
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/* VECTACTIVE */
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val = s->gic.running_irq[0];
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if (val == 1023) {
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val = 0;
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} else if (val >= 32) {
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val -= 16;
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}
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/* RETTOBASE */
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if (s->gic.running_irq[0] == 1023
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|| s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
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val |= (1 << 11);
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}
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/* VECTPENDING */
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if (s->gic.current_pending[0] != 1023)
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val |= (s->gic.current_pending[0] << 12);
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/* ISRPENDING */
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for (irq = 32; irq < s->num_irq; irq++) {
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if (s->gic.irq_state[irq].pending) {
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val |= (1 << 22);
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break;
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}
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}
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/* PENDSTSET */
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if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
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val |= (1 << 26);
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/* PENDSVSET */
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if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
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val |= (1 << 28);
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/* NMIPENDSET */
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if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
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val |= (1 << 31);
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return val;
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case 0xd08: /* Vector Table Offset. */
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cpu = ARM_CPU(current_cpu);
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return cpu->env.v7m.vecbase;
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case 0xd0c: /* Application Interrupt/Reset Control. */
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return 0xfa05000;
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case 0xd10: /* System Control. */
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/* TODO: Implement SLEEPONEXIT. */
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return 0;
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case 0xd14: /* Configuration Control. */
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/* TODO: Implement Configuration Control bits. */
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return 0;
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case 0xd24: /* System Handler Status. */
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val = 0;
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if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
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if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
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if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
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if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
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if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
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if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
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if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
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if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
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if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
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if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
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if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
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if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
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if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
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if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
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return val;
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case 0xd28: /* Configurable Fault Status. */
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/* TODO: Implement Fault Status. */
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qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");
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return 0;
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case 0xd2c: /* Hard Fault Status. */
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case 0xd30: /* Debug Fault Status. */
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case 0xd34: /* Mem Manage Address. */
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case 0xd38: /* Bus Fault Address. */
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case 0xd3c: /* Aux Fault Status. */
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/* TODO: Implement fault status registers. */
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qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");
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return 0;
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case 0xd40: /* PFR0. */
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return 0x00000030;
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case 0xd44: /* PRF1. */
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return 0x00000200;
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case 0xd48: /* DFR0. */
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return 0x00100000;
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case 0xd4c: /* AFR0. */
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return 0x00000000;
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case 0xd50: /* MMFR0. */
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return 0x00000030;
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case 0xd54: /* MMFR1. */
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return 0x00000000;
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case 0xd58: /* MMFR2. */
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return 0x00000000;
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case 0xd5c: /* MMFR3. */
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return 0x00000000;
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case 0xd60: /* ISAR0. */
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return 0x01141110;
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case 0xd64: /* ISAR1. */
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return 0x02111000;
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case 0xd68: /* ISAR2. */
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return 0x21112231;
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case 0xd6c: /* ISAR3. */
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return 0x01111110;
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case 0xd70: /* ISAR4. */
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return 0x01310102;
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/* TODO: Implement debug registers. */
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
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return 0;
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}
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}
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static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
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{
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ARMCPU *cpu;
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uint32_t oldval;
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switch (offset) {
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case 0x10: /* SysTick Control and Status. */
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oldval = s->systick.control;
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s->systick.control &= 0xfffffff8;
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s->systick.control |= value & 7;
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if ((oldval ^ value) & SYSTICK_ENABLE) {
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int64_t now = qemu_get_clock_ns(vm_clock);
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if (value & SYSTICK_ENABLE) {
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if (s->systick.tick) {
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s->systick.tick += now;
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qemu_mod_timer(s->systick.timer, s->systick.tick);
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} else {
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systick_reload(s, 1);
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}
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} else {
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qemu_del_timer(s->systick.timer);
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s->systick.tick -= now;
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if (s->systick.tick < 0)
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s->systick.tick = 0;
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}
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} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
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/* This is a hack. Force the timer to be reloaded
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when the reference clock is changed. */
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systick_reload(s, 1);
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}
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break;
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case 0x14: /* SysTick Reload Value. */
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s->systick.reload = value;
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break;
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case 0x18: /* SysTick Current Value. Writes reload the timer. */
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systick_reload(s, 1);
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s->systick.control &= ~SYSTICK_COUNTFLAG;
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break;
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case 0xd04: /* Interrupt Control State. */
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if (value & (1 << 31)) {
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
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}
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if (value & (1 << 28)) {
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
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} else if (value & (1 << 27)) {
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s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
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gic_update(&s->gic);
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}
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if (value & (1 << 26)) {
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armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
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} else if (value & (1 << 25)) {
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s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
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gic_update(&s->gic);
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}
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break;
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case 0xd08: /* Vector Table Offset. */
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cpu = ARM_CPU(current_cpu);
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cpu->env.v7m.vecbase = value & 0xffffff80;
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break;
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case 0xd0c: /* Application Interrupt/Reset Control. */
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if ((value >> 16) == 0x05fa) {
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if (value & 2) {
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qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
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}
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if (value & 5) {
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qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
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}
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}
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break;
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case 0xd10: /* System Control. */
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case 0xd14: /* Configuration Control. */
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/* TODO: Implement control registers. */
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qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");
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break;
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case 0xd24: /* System Handler Control. */
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/* TODO: Real hardware allows you to set/clear the active bits
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under some circumstances. We don't implement this. */
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s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
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s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
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s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
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break;
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case 0xd28: /* Configurable Fault Status. */
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case 0xd2c: /* Hard Fault Status. */
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case 0xd30: /* Debug Fault Status. */
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case 0xd34: /* Mem Manage Address. */
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case 0xd38: /* Bus Fault Address. */
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case 0xd3c: /* Aux Fault Status. */
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qemu_log_mask(LOG_UNIMP,
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"NVIC: fault status registers unimplemented\n");
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break;
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case 0xf00: /* Software Triggered Interrupt Register */
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if ((value & 0x1ff) < s->num_irq) {
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gic_set_pending_private(&s->gic, 0, value & 0x1ff);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"NVIC: Bad write offset 0x%x\n", offset);
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}
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}
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static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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nvic_state *s = (nvic_state *)opaque;
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uint32_t offset = addr;
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int i;
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uint32_t val;
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switch (offset) {
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case 0xd18 ... 0xd23: /* System Handler Priority. */
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val = 0;
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for (i = 0; i < size; i++) {
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val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8);
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}
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return val;
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case 0xfe0 ... 0xfff: /* ID. */
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if (offset & 3) {
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return 0;
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}
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return nvic_id[(offset - 0xfe0) >> 2];
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}
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if (size == 4) {
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return nvic_readl(s, offset);
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
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return 0;
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}
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static void nvic_sysreg_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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nvic_state *s = (nvic_state *)opaque;
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uint32_t offset = addr;
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int i;
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switch (offset) {
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case 0xd18 ... 0xd23: /* System Handler Priority. */
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for (i = 0; i < size; i++) {
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s->gic.priority1[(offset - 0xd14) + i][0] =
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(value >> (i * 8)) & 0xff;
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}
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gic_update(&s->gic);
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return;
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}
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if (size == 4) {
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nvic_writel(s, offset, value);
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return;
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
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}
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static const MemoryRegionOps nvic_sysreg_ops = {
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.read = nvic_sysreg_read,
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.write = nvic_sysreg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_nvic = {
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.name = "armv7m_nvic",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(systick.control, nvic_state),
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VMSTATE_UINT32(systick.reload, nvic_state),
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VMSTATE_INT64(systick.tick, nvic_state),
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VMSTATE_TIMER(systick.timer, nvic_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static void armv7m_nvic_reset(DeviceState *dev)
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{
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nvic_state *s = NVIC(dev);
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NVICClass *nc = NVIC_GET_CLASS(s);
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|
nc->parent_reset(dev);
|
|
/* Common GIC reset resets to disabled; the NVIC doesn't have
|
|
* per-CPU interfaces so mark our non-existent CPU interface
|
|
* as enabled by default, and with a priority mask which allows
|
|
* all interrupts through.
|
|
*/
|
|
s->gic.cpu_enabled[0] = true;
|
|
s->gic.priority_mask[0] = 0x100;
|
|
/* The NVIC as a whole is always enabled. */
|
|
s->gic.enabled = true;
|
|
systick_reset(s);
|
|
}
|
|
|
|
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
nvic_state *s = NVIC(dev);
|
|
NVICClass *nc = NVIC_GET_CLASS(s);
|
|
|
|
/* The NVIC always has only one CPU */
|
|
s->gic.num_cpu = 1;
|
|
/* Tell the common code we're an NVIC */
|
|
s->gic.revision = 0xffffffff;
|
|
s->num_irq = s->gic.num_irq;
|
|
nc->parent_realize(dev, errp);
|
|
if (error_is_set(errp)) {
|
|
return;
|
|
}
|
|
gic_init_irqs_and_distributor(&s->gic, s->num_irq);
|
|
/* The NVIC and system controller register area looks like this:
|
|
* 0..0xff : system control registers, including systick
|
|
* 0x100..0xcff : GIC-like registers
|
|
* 0xd00..0xfff : system control registers
|
|
* We use overlaying to put the GIC like registers
|
|
* over the top of the system control register region.
|
|
*/
|
|
memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
|
|
/* The system register region goes at the bottom of the priority
|
|
* stack as it covers the whole page.
|
|
*/
|
|
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
|
|
"nvic_sysregs", 0x1000);
|
|
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
|
|
/* Alias the GIC region so we can get only the section of it
|
|
* we need, and layer it on top of the system register region.
|
|
*/
|
|
memory_region_init_alias(&s->gic_iomem_alias, OBJECT(s),
|
|
"nvic-gic", &s->gic.iomem,
|
|
0x100, 0xc00);
|
|
memory_region_add_subregion_overlap(&s->container, 0x100,
|
|
&s->gic_iomem_alias, 1);
|
|
/* Map the whole thing into system memory at the location required
|
|
* by the v7M architecture.
|
|
*/
|
|
memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
|
|
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
|
|
}
|
|
|
|
static void armv7m_nvic_instance_init(Object *obj)
|
|
{
|
|
/* We have a different default value for the num-irq property
|
|
* than our superclass. This function runs after qdev init
|
|
* has set the defaults from the Property array and before
|
|
* any user-specified property setting, so just modify the
|
|
* value in the GICState struct.
|
|
*/
|
|
GICState *s = ARM_GIC_COMMON(obj);
|
|
/* The ARM v7m may have anything from 0 to 496 external interrupt
|
|
* IRQ lines. We default to 64. Other boards may differ and should
|
|
* set the num-irq property appropriately.
|
|
*/
|
|
s->num_irq = 64;
|
|
}
|
|
|
|
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
NVICClass *nc = NVIC_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
nc->parent_reset = dc->reset;
|
|
nc->parent_realize = dc->realize;
|
|
dc->vmsd = &vmstate_nvic;
|
|
dc->reset = armv7m_nvic_reset;
|
|
dc->realize = armv7m_nvic_realize;
|
|
}
|
|
|
|
static const TypeInfo armv7m_nvic_info = {
|
|
.name = TYPE_NVIC,
|
|
.parent = TYPE_ARM_GIC_COMMON,
|
|
.instance_init = armv7m_nvic_instance_init,
|
|
.instance_size = sizeof(nvic_state),
|
|
.class_init = armv7m_nvic_class_init,
|
|
.class_size = sizeof(NVICClass),
|
|
};
|
|
|
|
static void armv7m_nvic_register_types(void)
|
|
{
|
|
type_register_static(&armv7m_nvic_info);
|
|
}
|
|
|
|
type_init(armv7m_nvic_register_types)
|