Frédéric Pétrot a2f827ff4f target/riscv: accessors to registers upper part and 128-bit load/store ... Get function to retrieve the 64 top bits of a register, stored in the gprh field of the cpu state. Set function that writes the 128-bit value at once. The access to the gprh field can not be protected at compile time to make sure it is accessed only in the 128-bit version of the processor because we have no way to indicate that the misa_mxl_max field is const. The 128-bit ISA adds ldu, lq and sq. We provide support for these instructions. Note that (a) we compute only 64-bit addresses to actually access memory, cowardly utilizing the existing address translation mechanism of QEMU, and (b) we assume for now little-endian memory accesses. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-08 15:46:10 +10:00
..
trans_privileged.c.inc	target/riscv: Remove exit_tb and lookup_and_goto_ptr	2021-10-15 16:39:14 -07:00
trans_rva.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvb.c.inc	target/riscv: separation of bitwise logic and arithmetic helpers	2022-01-08 15:46:10 +10:00
trans_rvd.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvf.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: accessors to registers upper part and 128-bit load/store	2022-01-08 15:46:10 +10:00
trans_rvm.c.inc	target/riscv: Use gen_arith_per_ol for RVM	2021-10-22 23:35:43 +10:00
trans_rvv.c.inc	target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns	2022-01-08 15:46:09 +10:00
trans_rvzfh.c.inc	target/riscv: zfh: implement zfhmin extension	2021-12-20 14:51:36 +10:00