e06054368c
The include/hw/hw.h header only has a prototype for hw_error(), so it does not make sense to include this in files that do not use this function. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210326151848.2217216-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
216 lines
6.7 KiB
C
216 lines
6.7 KiB
C
/*
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* Microchip PolarFire SoC DDR Memory Controller module emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/misc/mchp_pfsoc_dmc.h"
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/* DDR SGMII PHY module */
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#define SGMII_PHY_IOC_REG1 0x208
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#define SGMII_PHY_TRAINING_STATUS 0x814
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#define SGMII_PHY_DQ_DQS_ERR_DONE 0x834
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#define SGMII_PHY_DQDQS_STATUS1 0x84c
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#define SGMII_PHY_PVT_STAT 0xc20
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static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t val = 0;
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static int training_status_bit;
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switch (offset) {
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case SGMII_PHY_IOC_REG1:
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/* See ddr_pvt_calibration() in HSS */
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val = BIT(4) | BIT(2);
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break;
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case SGMII_PHY_TRAINING_STATUS:
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/*
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* The codes logic emulates the training status change from
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* DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
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*
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* See ddr_setup() in mss_ddr.c in the HSS source codes.
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*/
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val = 1 << training_status_bit;
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training_status_bit = (training_status_bit + 1) % 5;
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break;
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case SGMII_PHY_DQ_DQS_ERR_DONE:
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/*
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* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
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* check that DQ/DQS training passed without error.
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*/
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val = 8;
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break;
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case SGMII_PHY_DQDQS_STATUS1:
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/*
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* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
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* check that DQ/DQS calculated window is above 5 taps.
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*/
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val = 0xff;
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break;
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case SGMII_PHY_PVT_STAT:
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/* See sgmii_channel_setup() in HSS */
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val = BIT(14) | BIT(6);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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break;
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}
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return val;
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}
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static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
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"(size %d, value 0x%" PRIx64
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", offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, value, offset);
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}
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static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
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.read = mchp_pfsoc_ddr_sgmii_phy_read,
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.write = mchp_pfsoc_ddr_sgmii_phy_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
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{
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MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
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memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
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&mchp_pfsoc_ddr_sgmii_phy_ops, s,
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"mchp.pfsoc.ddr_sgmii_phy",
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MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
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}
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static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
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dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
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}
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static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
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.name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
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.class_init = mchp_pfsoc_ddr_sgmii_phy_class_init,
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};
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static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
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{
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type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
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}
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type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
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/* DDR CFG module */
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#define CFG_MT_DONE_ACK 0x4428
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#define CFG_STAT_DFI_INIT_COMPLETE 0x10034
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#define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038
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static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t val = 0;
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switch (offset) {
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case CFG_MT_DONE_ACK:
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/* memory test in MTC_test() */
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val = BIT(0);
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break;
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case CFG_STAT_DFI_INIT_COMPLETE:
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/* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
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val = BIT(0);
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break;
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case CFG_STAT_DFI_TRAINING_COMPLETE:
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/* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
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val = BIT(0);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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break;
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}
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return val;
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}
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static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
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"(size %d, value 0x%" PRIx64
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", offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, value, offset);
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}
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static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
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.read = mchp_pfsoc_ddr_cfg_read,
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.write = mchp_pfsoc_ddr_cfg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
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{
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MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
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memory_region_init_io(&s->cfg, OBJECT(dev),
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&mchp_pfsoc_ddr_cfg_ops, s,
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"mchp.pfsoc.ddr_cfg",
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MCHP_PFSOC_DDR_CFG_REG_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
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}
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static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "Microchip PolarFire SoC DDR CFG module";
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dc->realize = mchp_pfsoc_ddr_cfg_realize;
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}
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static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
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.name = TYPE_MCHP_PFSOC_DDR_CFG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MchpPfSoCDdrCfgState),
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.class_init = mchp_pfsoc_ddr_cfg_class_init,
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};
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static void mchp_pfsoc_ddr_cfg_register_types(void)
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{
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type_register_static(&mchp_pfsoc_ddr_cfg_info);
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}
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type_init(mchp_pfsoc_ddr_cfg_register_types)
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