qemu-e2k

History

Peter Maydell ec53b45bcd exec.c: Drop TARGET_HAS_ICE define and checks The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org		2015-01-20 15:19:32 +00:00
..
cpu-qom.h	target-lm32: Use cpu_exec_interrupt qom hook	2014-09-25 18:54:22 +01:00
cpu.c	gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag	2014-10-06 14:25:43 +01:00
cpu.h	exec.c: Drop TARGET_HAS_ICE define and checks	2015-01-20 15:19:32 +00:00
gdbstub.c
helper.c	target-lm32: Use cpu_exec_interrupt qom hook	2014-09-25 18:54:22 +01:00
helper.h	tcg: Invert the inclusion of helper.h	2014-05-28 09:33:54 -07:00
lm32-semi.c	tcg: Invert the inclusion of helper.h	2014-05-28 09:33:54 -07:00
machine.c
Makefile.objs
op_helper.c	vl: allow other threads to do qemu_system_vmstop_request	2014-06-23 16:36:13 +08:00
README
TODO
translate.c	gen-icount: check cflags instead of use_icount global	2015-01-03 09:22:12 +01:00

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Semihosting
-----------
Semihosting on this target is supported. Some system calls like read, write
and exit are executed on the host if semihosting is enabled. See
target/lm32-semi.c for all supported system calls. Emulation aware programs
can use this mechanism to shut down the virtual machine and print to the
host console. See the tcg tests for an example.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);