57a0c9384c
This value is fully internal to qemu, and so is not a TARGET define. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "cpu_loop-common.h"
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#include "signal-common.h"
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#include "elf.h"
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#include "semihosting/common-semi.h"
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void cpu_loop(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr, signum, sigcode;
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target_ulong sigaddr;
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target_ulong ret;
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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signum = 0;
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sigcode = 0;
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sigaddr = 0;
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switch (trapnr) {
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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case RISCV_EXCP_U_ECALL:
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env->pc += 4;
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if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
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/* riscv_flush_icache_syscall is a no-op in QEMU as
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self-modifying code is automatically detected */
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ret = 0;
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} else {
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ret = do_syscall(env,
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env->gpr[(env->elf_flags & EF_RISCV_RVE)
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? xT0 : xA7],
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env->gpr[xA0],
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env->gpr[xA1],
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env->gpr[xA2],
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env->gpr[xA3],
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env->gpr[xA4],
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env->gpr[xA5],
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0, 0);
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}
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if (ret == -QEMU_ERESTARTSYS) {
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env->pc -= 4;
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} else if (ret != -QEMU_ESIGRETURN) {
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env->gpr[xA0] = ret;
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}
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if (cs->singlestep_enabled) {
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goto gdbstep;
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}
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break;
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case RISCV_EXCP_ILLEGAL_INST:
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signum = TARGET_SIGILL;
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sigcode = TARGET_ILL_ILLOPC;
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break;
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case RISCV_EXCP_BREAKPOINT:
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signum = TARGET_SIGTRAP;
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sigcode = TARGET_TRAP_BRKPT;
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sigaddr = env->pc;
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break;
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case RISCV_EXCP_SEMIHOST:
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env->gpr[xA0] = do_common_semihosting(cs);
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env->pc += 4;
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break;
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case EXCP_DEBUG:
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gdbstep:
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signum = TARGET_SIGTRAP;
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sigcode = TARGET_TRAP_BRKPT;
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break;
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default:
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EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
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trapnr);
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exit(EXIT_FAILURE);
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}
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if (signum) {
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target_siginfo_t info = {
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.si_signo = signum,
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.si_errno = 0,
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.si_code = sigcode,
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._sifields._sigfault._addr = sigaddr
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};
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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process_pending_signals(env);
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = env_cpu(env);
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TaskState *ts = cpu->opaque;
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struct image_info *info = ts->info;
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env->pc = regs->sepc;
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env->gpr[xSP] = regs->sp;
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env->elf_flags = info->elf_flags;
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if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
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error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
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exit(EXIT_FAILURE);
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}
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ts->stack_base = info->start_stack;
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ts->heap_base = info->brk;
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/* This will be filled in on the first SYS_HEAPINFO call. */
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ts->heap_limit = 0;
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}
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