57de3c1d35
This describes the I8042_MMIO device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-51-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/*
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* QEMU PS/2 Controller
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef HW_INPUT_I8042_H
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#define HW_INPUT_I8042_H
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#include "hw/isa/isa.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define I8042_KBD_IRQ 0
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#define I8042_MOUSE_IRQ 1
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typedef struct KBDState {
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uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
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uint8_t status;
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uint8_t mode;
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uint8_t outport;
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uint32_t migration_flags;
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uint32_t obsrc;
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bool outport_present;
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bool extended_state;
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bool extended_state_loaded;
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/* Bitmask of devices with data available. */
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uint8_t pending;
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uint8_t obdata;
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uint8_t cbdata;
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uint8_t pending_tmp;
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void *kbd;
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void *mouse;
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QEMUTimer *throttle_timer;
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qemu_irq irqs[2];
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qemu_irq a20_out;
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hwaddr mask;
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} KBDState;
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#define TYPE_I8042 "i8042"
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OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
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struct ISAKBDState {
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ISADevice parent_obj;
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KBDState kbd;
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bool kbd_throttle;
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MemoryRegion io[2];
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uint8_t kbd_irq;
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uint8_t mouse_irq;
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};
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/*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion defining the command/status/data
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* registers (access determined by mask property and access type)
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* + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
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* keyboard device has asserted its irq
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* + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
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* mouse device has asserted its irq
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* + Unnamed GPIO output 0-1: i8042 output irqs for keyboard (0) or mouse (1)
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*/
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#define TYPE_I8042_MMIO "i8042-mmio"
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OBJECT_DECLARE_SIMPLE_TYPE(MMIOKBDState, I8042_MMIO)
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struct MMIOKBDState {
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SysBusDevice parent_obj;
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KBDState kbd;
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uint32_t size;
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MemoryRegion region;
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};
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#define I8042_A20_LINE "a20"
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MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
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ram_addr_t size, hwaddr mask);
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void i8042_isa_mouse_fake_event(ISAKBDState *isa);
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void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
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static inline bool i8042_present(void)
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{
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bool amb = false;
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return object_resolve_path_type("", TYPE_I8042, &amb) || amb;
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}
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/*
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* ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
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* Flags, bit offset 1 - 8042.
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*/
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static inline uint16_t iapc_boot_arch_8042(void)
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{
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return i8042_present() ? 0x1 << 1 : 0x0 ;
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}
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#endif /* HW_INPUT_I8042_H */
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